Function declration can be as in verilog 1995/2001 or can be declared as in C or C++. In SystemVerilog following rules hold good for any Function declaration.

• Default Port Direction : Any port is seen as input, unless declared as other types. Following are port types
• input : copy value in at beginning
• output : copy value out at end
• inout : copy in at beginning and out at end
• ref : pass reference
• Default Data TYpe : Unless declared, data types of ports are of logic type.
• begin..end : There is no need to have begin, end, when more then one statement is used.
• return : A function can be terminated before enfunction, by usage of return statement.
• Variables : Systemverilog allows to have local static, or local dynamic variables.
• life time : SystemVerilog allows a function to static or automatic.
• Wire : Wire data type can not be used in port list;
• void : SystemVerilog allows functions to be declared as type void.

  1 module task_intro ();
  2 
  3 bit a ;
  4 
  5 initial begin
  6    #1  a = doInit(4,5);
  7    #1  a = doInit(9,6);
  8    #1  $finish;
  9 end
 10 
 11 function bit unsigned doInit (bit [3:0] count, add); 
 12   automatic reg [7:0] b;
 13   if (count > 5) begin
 14     $display ("@%g Returning from function", $time);
 15     return 0;
 16   end
 17   b = add;
 18   $display ("@%g Value passed is %d", $time, count + b);
 19   doInit = 1;
 20 endfunction
 21 
 22 endmodule

 @1 Value passed is   9
 @2 Returning from function

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