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  ../images/main/bullet_green_ball.gif Introduction

Task and Function are still same as in Verilog 2001, but SystemVerilog adds the ability to declare automatic variables within static tasks and functions, and static variables within automatic tasks and functions. Following are list of new addition

   

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  • Capabilities for declaring task and function ports like for module.
  • Passing arguments by reference instead of by value
  • Passing argument values by name instead of by position
  • Default argument values
  • Function output and inout ports
  • Void function
  • Multiple statements in a task or function without requiring a begin...end or fork...join block
  • Returning from a task or function before reaching the end of the task or function
  • Importing and exporting functions through the Direct Programming Interface (DPI)
   

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  ../images/main/bulllet_4dots_orange.gif Tasks

Task declration can be as in verilog 1995/2001 or can be declared as in C or C++. In SystemVerilog following rules hold good for any Task declaration.

   

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  • Default Port Direction : Any port is seen as input, unless declared as other types. Following are port types
    • input : copy value in at beginning
    • output : copy value out at end
    • inout : copy in at beginning and out at end
    • ref : pass reference
  • Default Data TYpe : Unless declared, data types of ports are of logic type.
  • begin..end : There is no need to have begin, end, when more then one statement is used.
  • return : A task can be terminated before entask, by usage of return statement.
  • Variables : Systemverilog allows to have local static, or local dynamic variables.
  • life time : SystemVerilog allows a task to static or automatic.
  • wire : Wire data type can not be used in port list;
   

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  ../images/main/bullet_star_pink.gif Example : Task
   

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  1 module task_intro ();
  2 
  3 initial begin
  4    #1  doInit(4,5);
  5    #1  doInit(9,6);
  6    #1  $finish;
  7 end
  8 
  9 task doInit (input bit [3:0] count, delay); 
 10   automatic reg [7:0] a;
 11   if (count > 5) begin
 12     $display ("@%g Returning from task", $time);
 13     return;
 14   end
 15   #(delay) $display ("@%g Value passed is %d", $time, count);
 16 endtask
 17 
 18 endmodule
You could download file task_intro.sv here
   

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  ../images/main/bullet_star_pink.gif Simulation Output
   

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 @6 Value passed is  4
 @7 Returning from task
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

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