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  ../images/main/bullet_star_pink.gif Transition bins creation

Transition coverage is used for checking if required transition happened, it is also used for checking if legal/illegal transition of values happened.

   

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In any coverage plan, it is very important that importance in given to transition coverage. In any testbench, which does not implement transition coverage, it is at best a poorly done functional coverage. Transition coverage has got ability to create scenarios which can not be captured by RTL coverage.

   

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Some of the examples of a transition coverage are

   

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  • Write followed by read to same address of memory
  • Jump instruction execution after a zero flag test in CPU
  • High priority frames followed by low priorit frames
  • cache miss followed by cache hit for a cache controller
   

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Note : It is very important that transition coverage be studied in detail and applied all verification env.

   

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  ../images/main/bullet_star_pink.gif Transition bins creation : Sequence

This is basic type of transition coverage bin. In this bin are created for one value transition to another value.

   

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WRITE => READ;

WRITE => READ => WRITE;

   

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  ../images/main/4blue_dots_bullets.gif Example : sequence bins creation
   

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  1 module test();
  2 
  3 logic [7:0] addr;
  4 reg ce;
  5 
  6 covergroup address_cov () @ (posedge ce);
  7   ADDRESS : coverpoint addr {
  8     // simple transition bin
  9     bins adr_0_to_1          = (0=>1);
 10     bins adr_1_to_0          = (1=>0);
 11     bins adr_1_to_2          = (1=>2);
 12     bins adr_2_to_1          = (1=>0);
 13     bins adr_0_1_2_3         = (0=>1=>2=>3);
 14     bins adr_1_4_7           = (1=>4=>7);
 15   }
 16 endgroup
 17 
 18 address_cov my_cov = new();
 19 
 20 initial begin
 21   ce   <= 0;
 22   addr <= 0;
 23   $monitor("ce %b addr 8'h%x",ce,addr);
 24   repeat (10) begin
 25     ce <= 1;
 26      #10 ;
 27     ce <= 0;
 28     addr ++;
 29      #10 ;
 30   end
 31 end
 32 
 33 endmodule
You could download file sequence_bin.sv here
   

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  ../images/main/4blue_dots_bullets.gif Simulation : sequence bins creation
   

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 ce 1 addr 8'h00
 ce 0 addr 8'h01
 ce 1 addr 8'h01
 ce 0 addr 8'h02
 ce 1 addr 8'h02
 ce 0 addr 8'h03
 ce 1 addr 8'h03
 ce 0 addr 8'h04
 ce 1 addr 8'h04
 ce 0 addr 8'h05
 ce 1 addr 8'h05
 ce 0 addr 8'h06
 ce 1 addr 8'h06
 ce 0 addr 8'h07
 ce 1 addr 8'h07
 ce 0 addr 8'h08
 ce 1 addr 8'h08
 ce 0 addr 8'h09
 ce 1 addr 8'h09
 ce 0 addr 8'h0a
   

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  ../images/main/4blue_dots_bullets.gif Report : sequence bins creation
   

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 ===========================================================
 Group : test::address_cov
 ===========================================================
 SCORE  WEIGHT GOAL   
  50.00 1      100    
 -----------------------------------------------------------
 Summary for Group   test::address_cov
 
 CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
 Variables 6        3         3       50.00   
 
 Variables for Group  test::address_cov
 
 VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT 
 ADDRESS  6        3         3       50.00   100  1      
 -----------------------------------------------------------
 Summary for Variable ADDRESS
 
 CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
 User Defined Bins 6        3         3       50.00   
 
 User Defined Bins for ADDRESS
 
 Uncovered bins
 
 NAME       COUNT AT LEAST NUMBER 
 adr_1_4_7  0     1        1      
 adr_2_to_1 0     1        1      
 adr_1_to_0 0     1        1      
 
 Covered bins
 
 NAME        COUNT AT LEAST  
 adr_0_1_2_3 1     1        
 adr_1_to_2  1     1        
 adr_0_to_1  1     1        
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com