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  What is logic synthesis ?
   
Life before HDL (Logic synthesis)
Impact of HDL and Logic synthesis.
What do we discuss here ?
   

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  Constructs Not Supported in Synthesis
   
Example of Non-Synthesizable Verilog construct.
 
Example - Initial Statement
Delays
Comparison to X and Z are always ignored
   

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  Constructs Supported in Synthesis
   
Operators and their Effect.
   

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  Logic Circuit Modeling
   
Combinational Circuit Modeling using assign
 
Tri-state buffer
Mux
Simple Concatenation
1 bit adder with carry
Multiply by 2
3 is to 8 decoder
Combinational Circuit Modeling using always
 
3 is to 8 decoder using always
Sequential Circuit Modeling
 
Simple Flip-Flop
   

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  Verilog Coding Style
   

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Google
 
Web www.asic-world.com

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com