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  ../images/main/bullet_green_ball.gif Constructs Not Supported in Synthesis
   

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Construct Type

Notes

initial

Used only in test benches.

events

Events make more sense for syncing test bench components.

real

Real data type not supported.

time

Time data type not supported.

force and release

Force and release of data types not supported.

assign and deassign

assign and deassign of reg data types is not supported. But assign on wire data type is supported.

fork join

Use nonblocking assignments to get same effect.

primitives

Only gate level primitives are supported.

table

UDP and tables are not supported.

   

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  ../images/main/bulllet_4dots_orange.gif Example of Non-Synthesizable Verilog construct.

Any code that contains the above constructs are not synthesizable, but within synthesizable constructs, bad coding could cause synthesis issues. I have seen codes where engineers code a flip-flop with both posedge of clock and negedge of clock in sensitivity list.

   

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Then we have another common type of code, where one reg variable is driven from more than one always block. Well it will surely cause synthesis error.

   

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  ../images/main/bullet_star_pink.gif Example - Initial Statement
   

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  1 module synthesis_initial(
  2 clk,q,d);
  3 input clk,d;
  4 output q;
  5 reg q;
  6 
  7 initial begin
  8  q <= 0;
  9 end 
 10 
 11 always @ (posedge clk)
 12 begin
 13  q <= d;
 14 end 
 15 
 16 endmodule
You could download file synthesis_initial.v here
   

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  ../images/main/bullet_star_pink.gif Delays

a = #10 b; This code is useful only for simulation purpose.

   

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Synthesis tool normally ignores such constructs, and just assumes that there is no #10 in above statement, thus treating above code as

   

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a = b;

   

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  ../images/main/bulllet_4dots_orange.gif Comparison to X and Z are always ignored
   

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  1 module synthesis_compare_xz (a,b);
  2 output a;
  3 input b;
  4 reg a;
  5   	 
  6 always @ (b)
  7 begin
  8   if ((b == 1'bz) || (b == 1'bx)) begin
  9     a = 1;
 10   end else begin
 11     a = 0;
 12   end
 13 end  
 14   	  	 
 15 endmodule
You could download file synthesis_compare_xz.v here
   

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There seems to be a common problem with all the design engineers new to hardware. They normally tend to compare variables with X and Z. In practice it is the worst thing to do, so please avoid comparing with X and Z. Limit your design to two states, 0 and 1. Use tri-state only at chip IO pads level. We will see this as an example in the next few pages.

   

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  ../images/main/bullet_green_ball.gif Constructs Supported in Synthesis

Verilog is such a simple language; you could easily write code which is easy to understand and easy to map to gates. Code which uses if, case statements is simple and cause little headaches with synthesis tools. But if you like fancy coding and like to have some trouble, ok don't be scared, you could use them after you get some experience with Verilog. Its great fun to use high level constructs, saves time.

   

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The most common way to model any logic is to use either assign statements or always blocks. An assign statement can be used for modeling only combinational logic and always can be used for modeling both combinational and sequential logic.

   

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Construct Type

Keyword or Description

Notes

ports

input, inout, output

Use inout only at IO level.

parameters

parameter

This makes design more generic

module definition

module

signals and variables

wire, reg, tri

Vectors are allowed

instantiation

module instances / primitive gate instances

E.g.- nand (out,a,b), bad idea to code RTL this way.

function and tasks

function , task

Timing constructs ignored

procedural

always, if, else, case, casex, casez

initial is not supported

procedural blocks

begin, end, named blocks, disable

Disabling of named blocks allowed

data flow

assign

Delay information is ignored

named Blocks

disable

Disabling of named block supported.

loops

for, while, forever

While and forever loops must contain @(posedge clk) or @(negedge clk)

   

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  ../images/main/bulllet_4dots_orange.gif Operators and their Effect.

One common problem that seems to occur is getting confused with logical and reduction operators. So watch out.

   

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Operator Type

Operator Symbol

Operation Performed

Arithmetic

*

Multiply

/

Division

+

Add

-

Subtract

%

Modulus

+

Unary plus

-

Unary minus

Logical

!

Logical negation

&&

Logical AND

||

Logical OR

Relational

>

Greater than

<

Less than

>=

Greater than or equal

<=

Less than or equal

Equality

==

Equality

!=

inequality

Reduction

&

Bitwise AND

~&

Bitwise NAND

|

Bitwise OR

~|

Bitwise NOR

^

Bitwise XOR

^~ ~^

Bitwise XNOR

Shift

>>

Right shift

<<

Left shift

Concatenation

{ }

Concatenation

Conditional

?

conditional

   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com