Gate Level Modeling

Gate Primitives

Transmission Gate Primitives

Switch Primitives

Logic Values and signal Strengths

Verilog Strength Levels

	Example : Strength Level
	Example 2 : Strength Level

Designing Using Primitives

AND Gate from NAND Gate

D-Flip flop from NAND Gate

Multiplexer from primitives

Gate and Switch delays

	Example - Single Delay
	Example - Two Delays
	Example - All Delays
	Example - Complex Example

N-Input Primitives

N-Output Primitives

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