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  ../images/main/bullet_green_ball.gif Designing Using Primitives

Designing using primitives is used only in library development, where the ASIC vendor provides the ASIC library Verilog description, using Verilog primitives and user defined primitives (UDP).

   

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  ../images/main/bulllet_4dots_orange.gif AND Gate from NAND Gate
   

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../images/verilog/and_from_nand.gif
   

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  ../images/main/bullet_star_pink.gif Code
   

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  1 // Structural model of AND gate from two NANDS 
  2 module and_from_nand();
  3 
  4 reg X, Y;
  5 wire F, W;
  6 // Two instantiations of the module NAND
  7 nand U1(W,X, Y);
  8 nand U2(F, W, W);
  9 
 10 // Testbench Code
 11 initial begin
 12   $monitor ("X = %b Y = %b F = %b", X, Y, F);
 13   X = 0;
 14   Y = 0;
 15    #1  X = 1;
 16    #1  Y = 1;
 17    #1  X = 0; 
 18    #1  $finish;
 19 end
 20 
 21 endmodule
You could download file and_from_nand.v here
   

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 X = 0 Y = 0 F = 0
 X = 1 Y = 0 F = 0
 X = 1 Y = 1 F = 1
 X = 0 Y = 1 F = 0
   

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  ../images/main/bulllet_4dots_orange.gif D-Flip flop from NAND Gate
   

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../images/verilog/d_from_nand.gif
   

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  ../images/main/bullet_star_pink.gif Verilog Code
   

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  1 module dff_from_nand();
  2 wire Q,Q_BAR;
  3 reg D,CLK;
  4 
  5 nand U1 (X,D,CLK) ;
  6 nand U2 (Y,X,CLK) ;
  7 nand U3 (Q,Q_BAR,X);
  8 nand U4 (Q_BAR,Q,Y);
  9 
 10 // Testbench of above code
 11 initial begin
 12   $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);
 13   CLK = 0;
 14   D = 0;
 15    #3  D = 1;
 16    #3  D = 0;
 17    #3  $finish;
 18 end	
 19 
 20 always  #2  CLK = ~CLK;
 21 
 22 endmodule
You could download file dff_from_nand.v here
   

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 CLK = 0 D = 0 Q = x Q_BAR = x
 CLK = 1 D = 0 Q = 0 Q_BAR = 1
 CLK = 1 D = 1 Q = 1 Q_BAR = 0
 CLK = 0 D = 1 Q = 1 Q_BAR = 0
 CLK = 1 D = 0 Q = 0 Q_BAR = 1
 CLK = 0 D = 0 Q = 0 Q_BAR = 1
   

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  ../images/main/bulllet_4dots_orange.gif Multiplexer from primitives
   

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../images/verilog/multiplexer.gif
   

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  ../images/main/bullet_star_pink.gif Verilog Code
   

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  1 module mux_from_gates ();
  2 reg c0,c1,c2,c3,A,B; 
  3 wire Y; 
  4 //Invert the sel signals 
  5 not (a_inv, A); 
  6 not (b_inv, B); 
  7 // 3-input AND gate 
  8 and (y0,c0,a_inv,b_inv); 
  9 and (y1,c1,a_inv,B); 
 10 and (y2,c2,A,b_inv); 
 11 and (y3,c3,A,B); 
 12 // 4-input OR gate 
 13 or (Y, y0,y1,y2,y3); 
 14 
 15 // Testbench Code goes here
 16 initial begin
 17   $monitor (
 18    "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b",
 19    c0, c1, c2, c3, A, B, Y);
 20   c0 = 0;
 21   c1 = 0;
 22   c2 = 0;
 23   c3 = 0;
 24   A = 0;
 25   B = 0;
 26    #1  A  = 1;
 27    #2  B  = 1;
 28    #4  A  = 0;
 29    #8  $finish;
 30 end
 31 
 32 always  #1  c0 = ~c0;
 33 always  #2  c1 = ~c1;
 34 always  #3  c2 = ~c2;
 35 always  #4  c3 = ~c3;
 36    
 37 endmodule 
You could download file mux_from_gates.v here
   

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 c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 0 Y = 0
 c0 = 1 c1 = 0 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0
 c0 = 0 c1 = 1 c2 = 0 c3 = 0 A = 1 B = 0 Y = 0
 c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 1 B = 1 Y = 0
 c0 = 0 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1
 c0 = 1 c1 = 0 c2 = 1 c3 = 1 A = 1 B = 1 Y = 1
 c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 1 B = 1 Y = 1
 c0 = 1 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1
 c0 = 0 c1 = 0 c2 = 0 c3 = 0 A = 0 B = 1 Y = 0
 c0 = 1 c1 = 0 c2 = 1 c3 = 0 A = 0 B = 1 Y = 0
 c0 = 0 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1
 c0 = 1 c1 = 1 c2 = 1 c3 = 0 A = 0 B = 1 Y = 1
 c0 = 0 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0
 c0 = 1 c1 = 0 c2 = 0 c3 = 1 A = 0 B = 1 Y = 0
 c0 = 0 c1 = 1 c2 = 0 c3 = 1 A = 0 B = 1 Y = 1
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com