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Equality Operators
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Like Verilog/SystemVerilog, Vera also supports Eqyality operators as shown below. |
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Operator
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Description
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a === b
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a equal to b, including x and z (Case equality)
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a !== b
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a not equal to b, including x and z (Case inequality)
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a == b
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a equal to b, result may be unknown (logical equality)
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a != b
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a not equal to b, result may be unknown (logical equality)
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a =?= b
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a equals b, x and z values are wildcards
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a !?= b
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a not equal to b, x and z values are wildcards
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- Operands are compared bit by bit, with zero filling if the two operands do not have the same length
- Result is 0 (false) or 1 (true)
- For the == and != operators, the result is x, if either operand contains an x or a z
- For the === and !== operators, bits with x and z are included in the comparison and must match for the result to be true
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Example : Equality Operators
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1 program equality {
2 // Case Equality
3 printf (" 4'bx001 === 4'bx001 = %b\n", (4'bx001 === 4'bx001));
4 printf (" 4'bx0x1 === 4'bx001 = %b\n", (4'bx0x1 === 4'bx001));
5 printf (" 4'bz0x1 === 4'bz0x1 = %b\n", (4'bz0x1 === 4'bz0x1));
6 printf (" 4'bz0x1 === 4'bz001 = %b\n", (4'bz0x1 === 4'bz001));
7 printf (" 4'b010x =?= 8'b0xx0010x = %b\n", (4'b010x =?= 8'b0xx0010x));
8 // Case Inequality
9 printf (" 4'bx0x1 !== 4'bx001 = %b\n", (4'bx0x1 ! == 4'bx001));
10 printf (" 4'bz0x1 !== 4'bz001 = %b\n", (4'bz0x1 ! == 4'bz001));
11 // Logical Equality
12 printf (" 5 == 10 = %b\n", (5 == 10));
13 printf (" 5 == 5 = %b\n", (5 == 5));
14 // Logical Inequality
15 printf (" 5 != 5 = %b\n", (5 ! = 5));
16 printf (" 5 != 6 = %b\n", (5 ! = 6));
17 }
You could download file equality.vr here
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Simulation : Equality Operators
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4'bx001 === 4'bx001 = 1
4'bx0x1 === 4'bx001 = 0
4'bz0x1 === 4'bz0x1 = 1
4'bz0x1 === 4'bz001 = 0
4'b010x =?= 8'b0xx0010x = 1
4'bx0x1 !== 4'bx001 = 1
4'bz0x1 !== 4'bz001 = 1
5 == 10 = 0
5 == 5 = 1
5 != 5 = 0
5 != 6 = 1
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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