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Default argument values
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To handle common cases or allow for unused arguments, SystemVerilog allows a task/function declaration to specify a default value for each singular argument. |
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Example - Default argument values
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1 module function_default_value ();
2
3 reg [7:0] data ;
4 reg parity_out;
5 time ltime;
6
7 function reg parity (reg [7:0] a, time b = 0, time c = 0);
8 parity = 0;
9 for (int i= 0; i < 8; i ++) begin
10 parity = parity ^ a[i];
11 end
12 endfunction
13
14 initial begin
15 parity_out = 0;
16 data = 0;
17 for (int i=250; i<256; i ++) begin
18 #5 data = i;
19 ltime = $time;
20 parity_out = parity (data);
21 parity_out = parity (data,,);
22 parity_out = parity (data,,10);
23 parity_out = parity (data,ltime,);
24 $display ("Data = %00000000b, Parity = %b", i, parity_out);
25 end
26 #10 $finish;
27 end
28
29 endmodule
You could download file function_default_value.sv here
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Simulation Output
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Data = 11111010, Parity = 0
Data = 11111011, Parity = 1
Data = 11111100, Parity = 0
Data = 11111101, Parity = 1
Data = 11111110, Parity = 1
Data = 11111111, Parity = 0
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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