SystemVerilog provides two means for passing arguments to functions and tasks, by value and by reference. Arguments can also be passed by name as well as by position. Task and function arguments can also be given default values, allowing the call to the task or function to not pass arguments.

Following are the ways of passing values to task and function in SystemVerilog.

• Pass by value
• Pass by reference
• Pass by name
• Pass by position
• default values
• Optional arguments.

In Verilog 1995/2001, this is how a argument is passed to a function or task. In this, argument value is copied to the task/function area.

  1 module function_by_value ();
  2 
  3 reg [7:0] data      ;
  4 reg       parity_out;
  5 integer   i         ;
  6 
  7 function parity;
  8  input [31:0] data;
  9  integer i;
 10  begin
 11   parity = 0;
 12   for (i= 0; i < 32; i = i + 1) begin
 13     parity = parity ^ data[i];
 14   end
 15  end
 16 endfunction
 17 
 18 initial begin    
 19   parity_out = 0;
 20   data = 0;
 21   for (i=250; i<256; i = i + 1) begin
 22     #5  data = i;
 23    parity_out = parity (data);
 24    $display ("Data = %b, Parity = %b", data, parity_out);
 25   end
 26    #10  $finish;
 27 end
 28 
 29 endmodule

 Data = 11111010, Parity = 0
 Data = 11111011, Parity = 1
 Data = 11111100, Parity = 0
 Data = 11111101, Parity = 1
 Data = 11111110, Parity = 1
 Data = 11111111, Parity = 0

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