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  ../images/main/bullet_green_ball.gif Introduction

In an always block which is used to model combinational logic, forgetting an else leads to an unintended latch. To avoid this mistake, SystemVerilog adds specialized always_comb and always_latch blocks, which indicate design intent to simulation, synthesis and formal verification tools. SystemVerilog also adds an always_ff block to indicate sequential logic.

   

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SystemVerilog has both static processes, introduced by always, initial or fork, and dynamic processes, introduced by built-in fork...join_any and fork...join_none.

   

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New features added SystemVerilog is as below

   

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  • always_combo
  • always_latch
  • always_ff
  • join_any
  • join_none
   

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For continous assignements SystemVerilog allows to drive other then net type to be driven or assigned using assign statement (Continuous assignments), Like reg or integer.

   

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  ../images/main/bulllet_4dots_orange.gif always_combo

SystemVerilog provides a special always_comb procedure for modeling combinational logic behavior.

   

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  • There is an inferred sensitivity list that includes the expressions defined.
  • The variables written on the left-hand side of assignments shall not be written to by any other process.
  • The procedure is automatically triggered once at time zero, after all initial and always blocks have been started so that the outputs of the procedure are consistent with the inputs.
   

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  ../images/main/bullet_star_pink.gif Example - always_combo
   

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  1 module always_comb_process();
  2 
  3 reg [7:0] sum,a,b;
  4 reg       parity;
  5 
  6 initial begin
  7   $monitor ("@%g a = %h b = %h sum = %h parity = %b", 
  8    $time, a, b, sum, parity);
  9    #1  a = 1;
 10    #1  b = 1;
 11    #5  a = 10;
 12    #1  $finish;
 13 end
 14 
 15 always_comb
 16 begin : ADDER
 17   sum = b + a;
 18   parity = ^sum;
 19 end
 20 
 21 endmodule
You could download file always_comb_process.sv here
   

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Simulator Output

   

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 @0 a = xx b = xx sum = xx parity = x
 @1 a = 01 b = xx sum = xx parity = x
 @2 a = 01 b = 01 sum = 02 parity = 1
 @7 a = 0a b = 01 sum = 0b parity = 1
   

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  ../images/main/bulllet_4dots_orange.gif always_latch

SystemVerilog also provides a special always_latch procedure for modeling latched logic behavior.

   

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  • The always_latch procedure determines its sensitivity and executes identically to the always_comb procedure.
   

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  ../images/main/bullet_star_pink.gif Example - always_latch
   

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  1 module always_latch_process();
  2 
  3 reg [7:0] sum,a,b;
  4 reg       parity;
  5 reg       enable = 0;
  6 
  7 initial begin
  8   $monitor ("@%g a = %h b = %h sum = %h parity = %b", 
  9     $time, a, b, sum, parity);
 10    #2  a = 1;
 11    #2  b = 1;
 12    #2  a = 10;
 13    #2  $finish;
 14 end
 15 
 16 always  #1  enable = ~enable;
 17 
 18 always_latch
 19 begin : ADDER
 20   if (enable) begin
 21     sum    <= b + a;
 22     parity <= ^(b + a);
 23   end
 24 end
 25 
 26 endmodule
You could download file always_latch_process.sv here
   

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Simulator Output

   

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 @0 a = xx b = xx sum = xx parity = x
 @2 a = 01 b = xx sum = xx parity = x
 @4 a = 01 b = 01 sum = xx parity = x
 @5 a = 01 b = 01 sum = 02 parity = 1
 @6 a = 0a b = 01 sum = 02 parity = 1
 @7 a = 0a b = 01 sum = 0b parity = 1
   

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  ../images/main/bulllet_4dots_orange.gif always_ff

The SystemVerilog always_ff procedure can be used to model synthesizable sequential logic behavior.

   

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  • The SystemVerilog always_ff procedure can be used to model synthesizable sequential logic behavior.
  • Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process.
   

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  ../images/main/bullet_star_pink.gif Example - always_ff
   

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  1 module always_ff_process();
  2 
  3 reg [7:0] sum,a,b;
  4 reg       parity;
  5 logic     clk = 0;
  6 reg       rst = 0;
  7 
  8 initial begin
  9   $monitor ("@%g clk = %b rst = %b a = %h b = %h sum = %h parity = %b", 
 10   $time, clk, rst, a, b, sum, parity);
 11    #1  rst = 1;
 12    #5  rst = 0;
 13    #2  a = 1;
 14    #2  b = 1;
 15    #2  a = 10;
 16    #2  $finish;
 17 end
 18 
 19 always  #1  clk ++;
 20 
 21 // use of iff makes sure that block does not get
 22 // triggered due to posedge of clk when rst == 1
 23 always_ff @(posedge clk iff rst == 0 or posedge rst)
 24 begin : ADDER
 25   if (rst) begin
 26     sum    <= 0;
 27     parity <= 0;
 28     $display ("Reset is asserted BLOCK 1");
 29   end else begin
 30     sum    <= b + a;
 31     parity <= ^(b + a);
 32   end
 33 end
 34 
 35 // To show how iff affected in earlier code
 36 always_ff @(posedge clk  or posedge rst)
 37 begin
 38   if (rst) begin
 39     $display ("Reset is asserted BLOCK 2");
 40   end 
 41 end
 42 
 43 endmodule
You could download file always_ff_process.sv here
   

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Simulator Output

   

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 @0 clk = 0 rst = 0 a = xx b = xx sum = xx parity = x
 Reset is asserted BLOCK 1
 Reset is asserted BLOCK 2
 @1 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
 @2 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
 Reset is asserted BLOCK 2
 @3 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
 @4 clk = 0 rst = 1 a = xx b = xx sum = 00 parity = 0
 Reset is asserted BLOCK 2
 @5 clk = 1 rst = 1 a = xx b = xx sum = 00 parity = 0
 @6 clk = 0 rst = 0 a = xx b = xx sum = 00 parity = 0
 @7 clk = 1 rst = 0 a = xx b = xx sum = xx parity = x
 @8 clk = 0 rst = 0 a = 01 b = xx sum = xx parity = x
 @9 clk = 1 rst = 0 a = 01 b = xx sum = xx parity = x
 @10 clk = 0 rst = 0 a = 01 b = 01 sum = xx parity = x
 @11 clk = 1 rst = 0 a = 01 b = 01 sum = 02 parity = 1
 @12 clk = 0 rst = 0 a = 0a b = 01 sum = 02 parity = 1
 @13 clk = 1 rst = 0 a = 0a b = 01 sum = 0b parity = 1
   

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  ../images/main/bulllet_4dots_orange.gif Continuous assignments

In verilog only net data types can be driven by continous assignment, In systemVerilog this restriction is removed and any data type can be driven using continuous assignment.

   

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  • Nets can be driven by multiple continuous assignments or by a mixture of primitives and continuous assignments.
  • Variables can only be driven by one continuous assignment or one primitive output.
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

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