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  ../images/main/bullet_green_ball.gif Introduction

Procedural statements in verilog are coded by following statements

   

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  • initial : enable this statement at the beginning of simulation and execute it only once
  • final : do this statement once at the end of simulation, new in SystemVerilog
  • always : always_comb, always_latch, always_ff, new in SystemVerilog
  • task : do these statements whenever the task is called
  • function : do these statements whenever the function is called and return a value
   

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SystemVerilog has the following types of control flow within a process

   

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  • Selection, loops and jumps : SystemVerilog adds c-Like do...while, break, continue
  • Task and function calls : SystemVerilog adds return
  • Sequential and parallel blocks
  • Timing control
   

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  ../images/main/bulllet_4dots_orange.gif Selection statements

In Verilog, an if (expression) is evaluated as a boolean, so that if the result of the expression is 0 or X, the test is considered false. SystemVerilog adds the keywords unique and priority, which can be used before an if. If either keyword is used, it shall be a run-time error for no condition to match unless there is an explicit else

   

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  • unique : A unique if indicates that there should not be any overlap in a series of if...else...if conditions.
  • priority: A priority if indicates that a series of if...else...if conditions shall be evaluated in the order listed.
   

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case selection statement

   

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The unique and priority keywords apply to the entire series of if...else...if conditions.

   

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In Verilog there are three types of case statements

   

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  • case
  • casex
  • casez
   

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In Systemverilog, each of above can be qualified with unique or priority, with following effect.

   

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  • unique : A unique case asserts that there are no overlapping case items and hence that it is safe for the case items to be evaluated in parallel.
  • priority case: A priority case acts only on first match.
   

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case inside selection statement

   

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The keyword inside can be used after the parenthesized expression to indicate a set membership case...inside statement. In a case...inside statement, the case expression shall be compared with each case item expression (open_range_list) using the set membership inside operator.

   

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  ../images/main/bullet_star_pink.gif Example - unique and priority
   

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  1 module unique_priority ();
  2 
  3 byte a = 0;
  4 
  5 // unique
  6 always @ (*)
  7 begin 
  8   unique if ((a==0) || (a==1)) begin
  9     $display("Unique if : 0 or 1"); 
 10   end else if (a == 2) begin
 11     $display("Unique if : 2"); 
 12   end else if (a == 4) begin
 13     $display("Unique if : 4"); 
 14   end
 15 end
 16 // priority
 17 always @ (*)
 18 begin
 19   priority if (a[2:1]==0) begin
 20     $display("Priority if : 0 or 1"); 
 21   end else if (a[2] == 0) begin
 22     $display("Priority if : 2 or 3"); 
 23   end else  begin
 24     $display("Priority if : 4 to 7"); 
 25   end
 26 end
 27 // unique case
 28 always @ (*)
 29 begin
 30   unique case(a) 
 31      0,1: $display("Unique Case 0 or 1");
 32      2  : $display("Unique Case 2");
 33      4  : $display("Unique Case 4");
 34   endcase
 35 end
 36 // priority case
 37 always @ (*)
 38 begin
 39   priority casez(a) 
 40     3'b00?: $display("Priority Casez 0 or 1");
 41     3'b0??: $display("Priority Casez 2 or 3");
 42   endcase
 43 end
 44 // unique case inside
 45 always @ (*)
 46 begin
 47   unique case(a) inside
 48      [0 : 3]: $display("Unique Case inside 0 to 3");
 49      2  : $display("Unique Case inside 2");
 50      4  : $display("Unique Case inside 4");
 51   endcase
 52 end
 53 
 54 initial begin
 55   repeat (7) begin
 56      #1  a ++;
 57   end
 58    #1  $finish;
 59 end
 60 
 61 endmodule
You could download file unique_priority.sv here
   

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Simulator Output

   

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 Unique if : 0 or 1
 Unique Case 0 or 1
 Priority Casez 0 or 1
 Unique Case inside 0 to 3
 Unique if : 2
 Unique Case 2
 Priority Casez 2 or 3
 Warning: More than one conditions match in 'unique case' statement.
         "unique_priority.sv", line 47,. 
         Line    48 &    49 are overlapping at time   2.
 Unique Case inside 0 to 3
 Priority if : 2 or 3
 Warning: No condition matches in 'unique if' statement.
         "unique_priority.sv", line 8, at time   3.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 30, at time   3.
 Priority Casez 2 or 3
 Unique Case inside 0 to 3
 Unique if : 4
 Unique Case 4
 Warning: No condition matches in 'priority case' statement.
         "unique_priority.sv", line 39, at time   4.
 Unique Case inside 4
 Priority if : 4 to 7
 Warning: No condition matches in 'unique if' statement.
         "unique_priority.sv", line 8, at time   5.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 30, at time   5.
 Warning: No condition matches in 'priority case' statement.
         "unique_priority.sv", line 39, at time   5.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 47, at time   5.
 Warning: No condition matches in 'unique if' statement.
         "unique_priority.sv", line 8, at time   6.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 30, at time   6.
 Warning: No condition matches in 'priority case' statement.
         "unique_priority.sv", line 39, at time   6.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 47, at time   6.
 Priority if : 4 to 7
 Warning: No condition matches in 'unique if' statement.
         "unique_priority.sv", line 8, at time   7.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 30, at time   7.
 Warning: No condition matches in 'priority case' statement.
         "unique_priority.sv", line 39, at time   7.
 Warning: No condition matches in 'unique case' statement.
         "unique_priority.sv", line 47, at time   7.
   

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  ../images/main/bulllet_4dots_orange.gif Loop statements

Verilog provides for, while, repeat and forever loops. SystemVerilog enhances the Verilog for loop, and adds a do...while loop and a foreach loop.

   

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  • do statement while(condition), is similar to C
  • SystemVerilog adds the ability to declare the for loop control variable within the for loop.
  • The foreach construct specifies iteration over the elements of an array.
   

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  ../images/main/bullet_star_pink.gif Example - do while loop
   

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  1 module while_loop ();
  2 
  3 byte a = 0;
  4 
  5 initial begin
  6   do begin
  7     $display ("Current value of a = %g", a);
  8     a ++;
  9   end while  (a < 10);
 10    #1  $finish;
 11 end
 12 
 13 endmodule
You could download file while_loop.sv here
   

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Simulator Output

   

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 Current value of a = 0
 Current value of a = 1
 Current value of a = 2
 Current value of a = 3
 Current value of a = 4
 Current value of a = 5
 Current value of a = 6
 Current value of a = 7
 Current value of a = 8
 Current value of a = 9
   

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  ../images/main/bullet_star_pink.gif Example - for loop
   

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  1 module for_loop ();
  2 
  3 initial begin
  4   fork
  5     for (int i = 0 ; i < 4; i ++) begin
  6        #1  $display ("First  -> Current value of i = %g", i);
  7     end
  8     for (int i = 4 ; i > 0; i --) begin
  9        #1  $display ("Second -> Current value of i = %g", i);
 10     end
 11   join
 12    #1  $finish;
 13 end
 14 
 15 endmodule
You could download file for_loop.sv here
   

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Simulator Output

   

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 First  -> Current value of i = 0
 Second -> Current value of i = 4
 First  -> Current value of i = 1
 Second -> Current value of i = 3
 First  -> Current value of i = 2
 Second -> Current value of i = 2
 First  -> Current value of i = 3
 Second -> Current value of i = 1
   

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  ../images/main/bullet_star_pink.gif Example - foreach loop
   

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  1 module foreach_loop ();
  2 
  3 byte a [10] = '{0,6,7,4,5,66,77,99,22,11};
  4 
  5 initial begin
  6   foreach (a[i]) begin
  7     $display ("Value of a is %g",i);
  8   end
  9    #1  $finish;
 10 end
 11 
 12 endmodule
You could download file foreach_loop.sv here
   

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Simulator Output

   

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 Value of a is 0
 Value of a is 1
 Value of a is 2
 Value of a is 3
 Value of a is 4
 Value of a is 5
 Value of a is 6
 Value of a is 7
 Value of a is 8
 Value of a is 9
   

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  ../images/main/bulllet_4dots_orange.gif Jump statements

SystemVerilog adds the C jump statements break, continue and return.

   

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  • break : out of loop as in C
  • continue : skip to end of loop (move to next loop value) as in C
  • return expression : exit from a function
  • return : exit from a task or void function
   

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The continue and break statements can only be used in a loop. The continue statement jumps to the end of the loop and executes the loop control if present. The break statement jumps out of the loop. The continue and break statements cannot be used inside a fork...join block to control a loop outside the fork...join block. The return statement can only be used in a task or function. In a function returning a value, the return must have an expression of the correct type.

   

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Note that SystemVerilog does not include the C goto statement.

   

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  ../images/main/bullet_star_pink.gif Example - break
   

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  1 module break_loop ();
  2 
  3 initial begin
  4   for (int i = 0 ; i < 10; i ++) begin
  5      #1  $display ("Current value of i = %g", i);
  6     if ( i == 5) begin
  7       $display ("Coming out of for loop");
  8       break;
  9     end
 10   end
 11    #1  $finish;
 12 end
 13 
 14 endmodule
You could download file break_loop.sv here
   

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Simulator Output

   

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 Current value of i = 0
 Current value of i = 1
 Current value of i = 2
 Current value of i = 3
 Current value of i = 4
 Current value of i = 5
 Coming out of for loop
   

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  ../images/main/bullet_star_pink.gif Example - continue
   

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  1 module continue_loop ();
  2 
  3 initial begin
  4   for (int i = 0 ; i < 10; i ++) begin
  5     if ( (i >= 5) && (i < 8)) begin
  6       $display ("Continue with next interation");
  7       continue;
  8     end
  9      #1  $display ("Current value of i = %g", i);
 10   end
 11    #1  $finish;
 12 end
 13 
 14 endmodule
You could download file continue_loop.sv here
   

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Simulator Output

   

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 Current value of i = 0
 Current value of i = 1
 Current value of i = 2
 Current value of i = 3
 Current value of i = 4
 Continue with next interation
 Continue with next interation
 Continue with next interation
 Current value of i = 8
 Current value of i = 9
   

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  ../images/main/bullet_star_pink.gif Example - return
   

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  1 module return_function ();
  2 
  3 initial begin
  4  printI();
  5   #1  $finish;
  6 end
  7 
  8 function void printI;
  9 begin
 10   for (int i = 0 ; i < 10; i ++) begin
 11     if (i >= 5) begin
 12       return; // no value returned
 13     end
 14     $display ("Current value of i = %g", i);
 15   end
 16 end
 17 endfunction
 18 
 19 
 20 endmodule
You could download file return_function.sv here
   

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Simulator Output

   

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 Current value of i = 0
 Current value of i = 1
 Current value of i = 2
 Current value of i = 3
 Current value of i = 4
   

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  ../images/main/bullet_star_pink.gif Example - return expression
   

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  1 module return_value_function ();
  2 
  3 
  4 initial begin
  5  $display ("Value returned from function = %g", printI());
  6   #1  $finish;
  7 end
  8 
  9 function int printI;
 10 begin
 11   for (int i = 0 ; i < 10; i ++) begin
 12     if (i >= 5) begin
 13       return i ; // value returned
 14     end
 15     $display ("Current value of i = %g", i);
 16   end
 17 end
 18 endfunction
 19 
 20 endmodule
You could download file return_value_function.sv here
   

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Simulator Output

   

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 Current value of i = 0
 Current value of i = 1
 Current value of i = 2
 Current value of i = 3
 Current value of i = 4
 Value returned from function = 5
   

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  ../images/main/bulllet_4dots_orange.gif Final blocks

The final block is like an initial block, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. A final block is typically used to display statistical information about the simulation.

   

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The only statements allowed inside a final block are those permitted inside a function declaration. This guarantees that they execute within a single simulation cycle. Unlike an initial block, the final block does not execute as a separate process; instead, it executes in zero time, the same as a function call.

   

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  ../images/main/bullet_star_pink.gif Example - final block
   

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  1 module final_block ();
  2 
  3 initial begin
  4   for (int i = 0 ; i < 10; i ++) begin
  5     if ( (i >= 5) && (i < 8)) begin
  6       $display ("@%g Continue with next interation", $time);
  7       continue;
  8     end
  9      #1  $display ("@%g Current value of i = %g", $time, i);
 10   end
 11    #1  $finish;
 12 end
 13 
 14 final begin
 15   $display ("Final block called at time %g", $time);
 16   $display ("---- We can not have delays in it ----");
 17 end
 18 
 19 endmodule
You could download file final_block.sv here
   

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Simulator Output

   

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 @1 Current value of i = 0
 @2 Current value of i = 1
 @3 Current value of i = 2
 @4 Current value of i = 3
 @5 Current value of i = 4
 @5 Continue with next interation
 @5 Continue with next interation
 @5 Continue with next interation
 @6 Current value of i = 8
 @7 Current value of i = 9
 Final block called at time 8
 ---- We can not have delays in it ----
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

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