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  ../images/main/bullet_green_ball.gif Introduction

SystemVerilog addes following new literal values to existing Verilog literals and improves some of the literals.

   

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  • time values
  • array values
  • structure values
  • Improvements to string literals.
   

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  ../images/main/bulllet_4dots_orange.gif Integer and Logic Literals

Literals integer and logic values can be sized and unsized, and follow the same rules as of Verilog 2001. Assignment of constant values to any variable can be single literal as shown below.

   

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  • '0 : Set all bits to 0
  • '1: Set all bits to 1
  • 'X or `x : Set all bits to x
  • `Z or `z : Set all bits to z
   

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  ../images/main/bullet_star_pink.gif Example - Integer Literals
   

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  1 `timescale 1ns/100ps
  2 module int_literals ();
  3 
  4 integer a;
  5 
  6 initial begin
  7   $monitor ("@ %gns a = %h", $time, a);
  8   a = '0;
  9    #1  a = 'x;
 10    #1  a = '1;
 11    #1  a = 'z;
 12    #1  a = 'b0;
 13    #1  a = 'bx;
 14    #1  a = 'b1;
 15    #1  a = 'bz;
 16    #1  $finish;
 17 end
 18 
 19 endmodule
You could download file int_literals.sv here
   

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  ../images/main/bullet_star_pink.gif Simulator Output
   

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 @ 0ns a = 00000000
 @ 1ns a = xxxxxxxx
 @ 2ns a = ffffffff
 @ 3ns a = zzzzzzzz
 @ 4ns a = 00000000
 @ 5ns a = xxxxxxxx
 @ 6ns a = 00000001
 @ 7ns a = zzzzzzzz
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

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