The event data type is same as that found in Verilog, with slight improvement. In SystemVerilog one event variable can be aliased to another event variable and also SystemVerilog allows a event variable to be always triggered.

Syntax : event variable_name [= initial_value];

Where initial_value can be another event variable if you want to alias, or null if you want variable_name to be triggered always. If you don't specify any initial value then it behave like a new event variable as in Verilog 2001.

  1 module events();
  2 // Declare a new event called ack
  3 event ack; 
  4 // Declare done as alias to ack 
  5 event done = ack; 
  6 // Event variable with no synchronization object
  7 event empty = null; 
  8 
  9 initial begin
 10    #1  -> ack;
 11    #1  -> empty;
 12    #1  -> done;
 13    #1  $finish;
 14 end
 15 
 16 always @ (ack)
 17 begin
 18   $display("ack event emitted");
 19 end
 20 
 21 always @ (done)
 22 begin
 23   $display("done event emitted");
 24 end
 25 
 26 /*
 27 always @ (empty)
 28 begin
 29   $display("empty event emitted");
 30 end
 31 */
 32 
 33 endmodule

 ack event emitted
 done event emitted
 ack event emitted
 done event emitted

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