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  ../images/main/bulllet_4dots_orange.gif Sequences

Sequence Layer uses the boolean layer to contruct valid sequence of events. The simplest sequential behaviors are linear. A linear sequence is a finite list of SystemVerilog boolean expressions in a linear order of increasing time. The linear sequence is said to match along a finite interval of consecutive clock ticks provided the first boolean expression evaluates to true at the first clock tick, the second boolean expression evaluates to true at the second clock tick, and so forth, up to and including the last boolean expression evaluating to true at the last clock tick. A single boolean expression is an example of a simple linear sequence, and it matches at a single clock tick provided the boolean expression evaluates to true at that clock tick.

   

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A sequence can be declared in following places

   

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  • module
  • interface
  • program
  • clocking block
  • package
   

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One sequence can call another sequence.

   

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Following are list of operators that sequence are build upon.

   

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  • ##
  • [* ]
  • [= ]
  • [-> ]
  • throughout
  • within Left
  • intersect
  • and
  • or
   

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  ../images/main/bullet_star_pink.gif ## Operator

A ## followed by a number or range specifies the delay from the current clock tick to the beginning of the sequence that follows. The delay ##1 indicates that the beginning of the sequence that follows is one clock tick later than the current clock tick. The delay ##0 indicates that the beginning of the sequence that follows is at the same clock tick as the current clock tick.

   

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  • req ##1 gnt : Means gnt happens one clock cycle later of req.
  • req ##0 gnt : Means gnt happens on same edge as req getting asserted. Normally this is used for merging two sequence.
  • req ##[0:3] gnt : Means gnt will be asserted 0 to 3 clock cycles after req is asserted.
   

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Note : Variables can be used instead of constants for delay.

   

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  ../images/main/4blue_dots_bullets.gif Example : ## Operator
   

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   1 //+++++++++++++++++++++++++++++++++++++++++++++++++
   2 //   DUT With assertions
   3 //+++++++++++++++++++++++++++++++++++++++++++++++++
   4 module hash_sequence();
   5 
   6 logic clk = 0;
   7 always  #1  clk ++;
   8 
   9 logic [2:0] req,gnt;
  10 logic reset;
  11 //=================================================
  12 // Shows basic usage of ## delay operator
  13 //=================================================
  14 sequence req_gnt_1clock_seq;
  15   req[0]  ##1  gnt[0];
  16 endsequence
  17 //=================================================
  18 // Shows range usage of ## delay operator
  19 //=================================================
  20 sequence req_gnt_3to5clock_seq;
  21   req[1] ##[3:5] gnt[1];
  22 endsequence
  23 //=================================================
  24 // Shows zero delay usage of ## delay operator
  25 //=================================================
  26 sequence req_gnt_0clock_seq;
  27   req[2]  ##0  gnt[2];
  28 endsequence
  29 //=================================================
  30 // Shows sequence called within sequence 
  31 //=================================================
  32 sequence master_seq;
  33   req_gnt_1clock_seq  ##1  req_gnt_3to5clock_seq  ##1  req_gnt_0clock_seq;
  34 endsequence
  35 //=================================================
  36 //  Declare property for each of sequence
  37 //  We may use more then one seuqnce in a property
  38 //=================================================
  39 property req_gnt_1clock_prop;
  40   @ (posedge clk)
  41   disable iff (reset)
  42      req[0] |-> req_gnt_1clock_seq;
  43 endproperty
  44 
  45 property req_gnt_3to5clock_prop;
  46   @ (posedge clk)
  47   disable iff (reset)
  48      req[1] |-> req_gnt_3to5clock_seq;
  49 endproperty
  50 
  51 property req_gnt_0clock_prop;
  52   @ (posedge clk)
  53   disable iff (reset)
  54      req[2] |-> req_gnt_0clock_seq;
  55 endproperty
  56 
  57 property master_prop;
  58   @ (posedge clk)
  59   disable iff (reset)
  60      req[0] |-> master_seq;
  61 endproperty
  62   
  63 //=================================================
  64 // Assertion Directive Layer
  65 //=================================================
  66 req_gnt_1clock_assert    : assert property (req_gnt_1clock_prop);
  67 req_gnt_3to5clock_assert : assert property (req_gnt_3to5clock_prop);
  68 req_gnt_0clock_assert    : assert property (req_gnt_0clock_prop);
  69 master_assert            : assert property (master_prop);
  70 
  71 //=================================================
  72 // Drive the input vectors to test assetion
  73 //=================================================
  74 initial begin
  75   // Init all the values
  76   reset  <= 0;
  77   for (int i = 0; i < 3; i++) begin
  78     req[i] <= 0;
  79     gnt[i] <= 0;
  80   end
  81   @ (posedge clk);
  82   req[0] <= 1;
  83   @ (posedge clk);
  84   gnt[0] <= 1;
  85   req[0] <= 0;
  86   @ (posedge clk);
  87   gnt[0] <= 0;
  88   req[1] <= 1;
  89   @ (posedge clk);
  90   req[1] <= 0;
  91   repeat(3) @ (posedge clk);
  92   gnt[1] <= 1;
  93   @ (posedge clk);
  94   gnt[1] <= 0;
  95   req[2] <= 1;
  96   gnt[2] <= 1;
  97   @ (posedge clk);
  98   req[2] <= 0;
  99   gnt[2] <= 0;
 100   // Cause assertion to fail
 101   @ (posedge clk);
 102   req[0] <= 1;
 103   repeat(2) @ (posedge clk);
 104   gnt[0] <= 1;
 105   req[0] <= 0;
 106    #30  $finish;
 107 end
 108 
 109 endmodule
You could download file hash_sequence.sv here
   

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  ../images/main/4blue_dots_bullets.gif Simulation : ## Operator
   

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 Error: Assertion error.
 Time: 23 ns Started: 21 ns  Scope: 
 hash_sequence.req_gnt_1clock_assert File: hash_sequence.sv Line: 63
 Error: Assertion error.
 Time: 23 ns Started: 21 ns  Scope: 
 hash_sequence.master_assert File: hash_sequence.sv Line: 66
 Error: Assertion error.
 Time: 27 ns Started: 23 ns  Scope: 
 hash_sequence.master_assert File: hash_sequence.sv Line: 66
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com