expect is same as assert in syntax, but expect is used inside a procedural block, and it waits till a property evalutes to true or false.

Below example shows how a expect is used and its possible syntax.

  1 module expect_assertion;
  2 
  3 logic clk = 0;
  4 always  #1  clk ++;
  5 
  6 logic a, b,c;
  7 
  8 default clocking myclk @ (posedge clk);
  9 
 10 endclocking
 11 
 12 initial begin 
 13   a <= 0;
 14   b <= 0;
 15   c <= 0;
 16    ##1 ;
 17   a <= 1;
 18    ##1 ;
 19   a <= 0;
 20   b <= 1;
 21    ##1 ;
 22   b <= 0;
 23   c <= 0;
 24    ##1 ;
 25   c <= 0;
 26    ##20000  $finish;
 27 end
 28 
 29 initial begin
 30    ##1 ;
 31   // Wait for the sequence if pass, terminate sim
 32   expect ( @ (posedge clk) a  ##1  b  ##1  c  ##1   ! c)
 33      $finish;
 34    else
 35      $error ("Something is wrong");
 36 end
 37   
 38 endmodule

 Something is wrong
 Simulation complete via $finish(1) at time 40007 NS + 0

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com