Resolved vector signals have same property as Resolved Logic Vectors. Resolved vector signals are used for connecting two resolved logic vector ports. One key issue is, Resolved Vector signals should not be driven outside a process/methods.

  1 #include <systemc.h>
  2 
  3 SC_MODULE(resolve) {
  4   sc_in_rv<1>  in;
  5   sc_out_rv<1> out;
  6   sc_inout_rv<4> inout;
  7 
  8   void body () {
  9     out.write(in);
 10     if (in.read() == 1) {
 11       out.write(1);
 12       inout.write(rand());
 13     } else {
 14       out.write("z");
 15       inout.write("zzzz");
 16     }
 17   }
 18  
 19   SC_CTOR(resolve) {
 20     SC_METHOD(body);
 21       sensitive << in;
 22   }
 23 };
 24 
 25 // Testbench to generate test vectors
 26 int sc_main (int argc, char* argv[]) {
 27   sc_signal_rv<1> in1,in2;
 28   sc_signal_rv<1> out;
 29   sc_signal_rv<4> inout;
 30 
 31   resolve rs1("RESOLVE1");
 32     rs1.in(in1);
 33     rs1.out(out);
 34     rs1.inout(inout);
 35   resolve rs2("RESOLVE2");
 36     rs2.in(in2);
 37     rs2.out(out);
 38     rs2.inout(inout);
 39 
 40   sc_start(0);
 41   // Open VCD file
 42   sc_trace_file *wf = sc_create_vcd_trace_file("resolve");
 43     sc_trace(wf, in1, "in1");
 44     sc_trace(wf, in2, "in2");
 45     sc_trace(wf, out, "out");
 46     sc_trace(wf, inout, "inout");
 47   // Start the testing here
 48   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 49     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 50   sc_start(1);
 51   in1 = 0;
 52   in2 = 0;
 53   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 54     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 55   sc_start(1);
 56   in1 = 1;
 57   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 58     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 59   sc_start(1);
 60   in1 = 0;
 61   in2 = 1;
 62   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 63     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 64   sc_start(1);
 65   in2 = 0;
 66   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 67     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 68   sc_start(1);
 69   in1 = 1;
 70   in2 = 1;
 71   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 72     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 73   sc_start(1);
 74   in1 = 0;
 75   in2 = 0;
 76   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 77     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 78   sc_start(2);
 79   cout << "@" << sc_time_stamp() <<" in1 : " << in1
 80     <<" in2 : " << in2 <<" out : " << out <<" inout : " << inout << endl;
 81   sc_close_vcd_trace_file(wf);
 82   return 0;// Terminate simulation
 83 };

              SystemC 2.0.1 --- Oct  6 2006 19:17:37
         Copyright (c) 1996-2002 by all Contributors
                     ALL RIGHTS RESERVED
 @0 s in1 : X in2 : X out : Z inout : ZZZZ
 WARNING: Default time step is used for VCD tracing.
 @1 ns in1 : X in2 : X out : Z inout : ZZZZ
 @2 ns in1 : 0 in2 : 0 out : Z inout : ZZZZ
 @3 ns in1 : 1 in2 : 0 out : 1 inout : 0111
 @4 ns in1 : 0 in2 : 1 out : 1 inout : 0110
 @5 ns in1 : 0 in2 : 0 out : Z inout : ZZZZ
 @6 ns in1 : 1 in2 : 1 out : 1 inout : X0X1
 @8 ns in1 : 0 in2 : 0 out : Z inout : ZZZZ

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Deepak Kumar Tala - All rights reserved

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