1 //-----------------------------------------------------
  2 // Design Name : up_counter_load
  3 // File Name   : up_counter_load.sv
  4 // Function    : Up counter with load
  5 // Coder      : Deepak
  6 //-----------------------------------------------------
  7 module up_counter_load    (
  8 output  reg  [7:0]  out      ,  // Output of the counter
  9 input   wire [7:0]  data     ,  // Parallel load for the counter
 10 input   wire        load     ,  // Parallel load enable
 11 input   wire        enable   ,  // Enable counting
 12 input   wire        clk      ,  // clock input
 13 input   wire        reset       // reset input
 14 );
 15 //-------------Code Starts Here-------
 16 always_ff @ (posedge clk)
 17 if (reset) begin
 18   out <= 8'b0 ;
 19 end else if (load) begin
 20   out <= data;
 21 end else if (enable) begin
 22   out <= ++;
 23 end
 24     
 25 endmodule  

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Deepak Kumar Tala - All rights reserved

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