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Introduction
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Let's assume that we have a design which requires us to have counters of various width, but with the same functionality. Maybe we can assume that we have a design which requires lots of instants of different depth and width of RAMs of similar functionality. Normally what we do is creating counters of different widths and then use them. The same rule applies to the RAM we talked about. |
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But Verilog provides a powerful way to overcome this problem: it provides us with something called parameter; these parameters are like constants local to that particular module. |
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We can override the default values, either using defparam or by passing a new set of parameters during instantiation. We call this parameter overriding. |
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Parameters
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A parameter is defined by Verilog as a constant value declared within the module structure. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation. |
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- Defined inside a module.
- Local scope.
- Maybe overridden at instantiation time.
- If multiple parameters are defined, they must be overridden in the order they were defined. If an overriding value is not specified, the default parameter declaration values are used.
- Maybe changed using the defparam statement.
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Parameter Override using defparam
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1 module secret_number;
2 parameter my_secret = 0;
3
4 initial begin
5 $display("My secret number is %d", my_secret);
6 end
7
8 endmodule
9
10 module defparam_example();
11
12 defparam U0.my_secret = 11;
13 defparam U1.my_secret = 22;
14
15 secret_number U0();
16 secret_number U1();
17
18 endmodule
You could download file defparam_example.v here
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Parameter Override during instantiating.
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1 module secret_number;
2 parameter my_secret = 0;
3
4 initial begin
5 $display("My secret number in module is %d", my_secret);
6 end
7
8 endmodule
9
10 module param_overide_instance_example();
11
12 secret_number #(11) U0();
13 secret_number #(22) U1();
14
15 endmodule
You could download file param_overide_instance_example.v here
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Passing more than one parameter
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1 module ram_sp_sr_sw (
2 clk , // Clock Input
3 address , // Address Input
4 data , // Data bi-directional
5 cs , // Chip Select
6 we , // Write Enable/Read Enable
7 oe // Output Enable
8 );
9
10 parameter DATA_WIDTH = 8 ;
11 parameter ADDR_WIDTH = 8 ;
12 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
13 // Actual code of RAM here
14
15 endmodule
You could download file param_more_then_one.v here
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When instantiating more than the one parameter, parameter values should be passed in the order they are declared in the sub module. |
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1 module ram_controller ();//Some ports
2
3 // Controller Code
4
5 ram_sp_sr_sw #(16,8,256) ram(clk,address,data,cs,we,oe);
6
7 endmodule
You could download file param_more_then_one1.v here
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Verilog 2001
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In Verilog 2001, the code above will work, but the new feature makes the code more readable and error free. |
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1 module ram_controller ();//Some ports
2
3 ram_sp_sr_sw #(
4 .DATA_WIDTH(16),
5 .ADDR_WIDTH(8),
6 .RAM_DEPTH(256)) ram(clk,address,data,cs,we,oe);
7
8 endmodule
You could download file param_more_then_one2.v here
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Was this copied from VHDL? |
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