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  ../images/main/bulllet_4dots_orange.gif FileIO

This is one of the good features that was added to Verilog 2001. In Verilog 1995, file IO was limited to reading hex files into memory array using readmemh and writing file using $display and $monitor.

   

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But in Verilog 2001, following operations can performed.

   

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  • C or C++ type file operation (like checking end of file).
  • Reading charaters from file from a fixed location.
  • Reading a formated lines in file.
  • Writing a formated lines into file.
   

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Opening a file

A file can be opened for reading or writing, and the syntax is as below.

   

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file = $fopen("filename",r); // For reading

file = $fopen("filename",w); // For writing

   

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Below table shows all the possible $fopen modes.

   

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"r" or "rb"

Open for reading

"w" or "wb"

Truncate to zero length or create for writing

"a" or "ab"

Append (open for writing at end of file)

"r+", "r+b", or "rb+"

Open for update (reading and writing)

"w+", "w+b", or "wb+"

Truncate or create for update

"a+", "a+b", or "ab+"

Append; Open or create for update at end-of-file

   

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Closing a file

A file can be cloases as below.

   

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$fclose(file); // Here file is the handle which was assigned with $fopen

   

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Reading data from a file

Verilog 2001 FileIO supports following ways of reading a file.

   

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  • Reading a character at a time with $fgetc.
  • Reading a line at a time with $fgets.
  • Reading formatted data with $fscanf. The $fscanf function reads characters from the file specified by the file descriptor, interprets them according to a format, and stores the results in its arguments.
  • Reading binary data with $fread. The $fread function reads binary data from the file specified by the file descriptor into a register or into a memory.
   

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For details of each of the function please refer to VErilog 2001 LRM.

   

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Below example shows how to Verilog fileio in a verification env.

   

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  ../images/main/bullet_star_pink.gif Example : Verilog FileIO
   

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  1 module fileio;
  2 
  3 integer in,out,mon;
  4 reg clk;
  5 
  6 reg  enable;
  7 wire valid;
  8 reg [31:0] din;
  9 reg [31:0] exp;
 10 wire [31:0] dout;
 11 integer statusI,statusO;
 12 
 13 dut dut (clk,enable,din,dout,valid);
 14 
 15 initial begin
 16   clk = 0;
 17   enable  = 0;
 18   din = 0;
 19   exp = 0;
 20   in  = $fopen("input.txt","r");
 21   out = $fopen("output.txt","r");
 22   mon = $fopen("monitor.txt","w");
 23 end
 24 
 25 always  #  1 clk = ~clk;
 26 
 27 // DUT input driver code
 28 initial begin
 29     repeat (10) @ (posedge clk);
 30     while ( ! $feof(in)) begin
 31       @ (negedge clk);
 32       enable = 1;
 33       statusI = $fscanf(in,"%h %h\n",din[31:16],din[15:0]);
 34       @ (negedge clk);
 35       enable = 0;
 36     end
 37     repeat (10) @ (posedge clk);
 38     $fclose(in);
 39     $fclose(out);
 40     $fclose(mon);
 41      #100  $finish;
 42 end
 43 
 44 // DUT output monitor and compare logic
 45 always @ (posedge clk)
 46  if (valid) begin
 47    $fwrite(mon,"%h %h\n",dout[31:16],dout[15:0]);
 48    statusO = $fscanf(out,"%h %h\n",exp[31:16],exp[15:0]);
 49    if (dout  ! == exp) begin
 50      $display("%0dns Error : input and output does not match",$time);
 51      $display("       Got  %h",dout);
 52      $display("       Exp  %h",exp);
 53    end else begin
 54      $display("%0dns Match : input and output match",$time);
 55      $display("       Got  %h",dout);
 56      $display("       Exp  %h",exp);
 57    end
 58  end
 59 
 60 endmodule
 61 
 62 // DUT model
 63 module dut(
 64   input wire clk,enable,
 65   input wire [31:0] din,
 66   output reg [31:0] dout,
 67   output reg       valid
 68 );
 69 
 70 always @ (posedge clk)
 71   begin
 72     dout  <= din + 1;
 73     valid  <= enable;
 74   end
 75 
 76 endmodule
You could download file compare.v here
   

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  ../images/main/bullet_star_pink.gif Input File
   

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 0456 08a0
 0457 08a1
 0458 08a2
 0459 08a3
 045a 08a4
 045b 08a5
 045c 08a6
 045d 08a7
 045e 08a8
 045f 08a9
 0460 08aa
 0461 08ab
 0462 08ac
 0463 08ad
 0464 08ae
 0465 08af
 0466 08b0
 0467 08b1
 0468 08b2
 0469 08b3
 046a 08b4
 046b 08b5
 046c 08b6
 046d 08b7
 046e 08b8
 046f 08b9
 0470 08ba
 0471 08bb
 0472 08bc
 0473 08bd
   

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  ../images/main/bullet_star_pink.gif Expected Output File
   

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 0456 08a1
 0457 08a2
 0458 08a3
 0459 08a4
 045a 08a5
 045b 08a6
 045c 08a7
 045d 08a8
 045e 08a9
 045f 08aa
 0460 08ab
 0461 08ac
 0462 08ad
 0463 08ae
 0464 08af
 0465 08b0
 0466 08b1
 0467 08b2
 0468 08b3
 0469 08b4
 046a 08b5
 046b 08b6
 046c 08b7
 046d 08b8
 046e 08b9
 046f 08ba
 0470 08bb
 0471 08bc
 0472 08bd
 0473 08be
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com