This is one of the good features that was added to Verilog 2001. In Verilog 1995, file IO was limited to reading hex files into memory array using readmemh and writing file using $display and $monitor.

But in Verilog 2001, following operations can performed.

• C or C++ type file operation (like checking end of file).
• Reading charaters from file from a fixed location.
• Reading a formated lines in file.
• Writing a formated lines into file.

Opening a file

A file can be opened for reading or writing, and the syntax is as below.

file = $fopen("filename",r); // For reading

file = $fopen("filename",w); // For writing

Below table shows all the possible $fopen modes.

Closing a file

A file can be cloases as below.

$fclose(file); // Here file is the handle which was assigned with $fopen

Reading data from a file

Verilog 2001 FileIO supports following ways of reading a file.

• Reading a character at a time with $fgetc.
• Reading a line at a time with $fgets.
• Reading formatted data with $fscanf. The $fscanf function reads characters from the file specified by the file descriptor, interprets them according to a format, and stores the results in its arguments.
• Reading binary data with $fread. The $fread function reads binary data from the file specified by the file descriptor into a register or into a memory.

For details of each of the function please refer to VErilog 2001 LRM.

Below example shows how to Verilog fileio in a verification env.

  1 module fileio;
  2 
  3 integer in,out,mon;
  4 reg clk;
  5 
  6 reg  enable;
  7 wire valid;
  8 reg [31:0] din;
  9 reg [31:0] exp;
 10 wire [31:0] dout;
 11 integer statusI,statusO;
 12 
 13 dut dut (clk,enable,din,dout,valid);
 14 
 15 initial begin
 16   clk = 0;
 17   enable  = 0;
 18   din = 0;
 19   exp = 0;
 20   in  = $fopen("input.txt","r");
 21   out = $fopen("output.txt","r");
 22   mon = $fopen("monitor.txt","w");
 23 end
 24 
 25 always  #  1 clk = ~clk;
 26 
 27 // DUT input driver code
 28 initial begin
 29     repeat (10) @ (posedge clk);
 30     while ( ! $feof(in)) begin
 31       @ (negedge clk);
 32       enable = 1;
 33       statusI = $fscanf(in,"%h %h\n",din[31:16],din[15:0]);
 34       @ (negedge clk);
 35       enable = 0;
 36     end
 37     repeat (10) @ (posedge clk);
 38     $fclose(in);
 39     $fclose(out);
 40     $fclose(mon);
 41      #100  $finish;
 42 end
 43 
 44 // DUT output monitor and compare logic
 45 always @ (posedge clk)
 46  if (valid) begin
 47    $fwrite(mon,"%h %h\n",dout[31:16],dout[15:0]);
 48    statusO = $fscanf(out,"%h %h\n",exp[31:16],exp[15:0]);
 49    if (dout  ! == exp) begin
 50      $display("%0dns Error : input and output does not match",$time);
 51      $display("       Got  %h",dout);
 52      $display("       Exp  %h",exp);
 53    end else begin
 54      $display("%0dns Match : input and output match",$time);
 55      $display("       Got  %h",dout);
 56      $display("       Exp  %h",exp);
 57    end
 58  end
 59 
 60 endmodule
 61 
 62 // DUT model
 63 module dut(
 64   input wire clk,enable,
 65   input wire [31:0] din,
 66   output reg [31:0] dout,
 67   output reg       valid
 68 );
 69 
 70 always @ (posedge clk)
 71   begin
 72     dout  <= din + 1;
 73     valid  <= enable;
 74   end
 75 
 76 endmodule

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Deepak Kumar Tala - All rights reserved

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