Technical This section is about technical questions that are asked frequently. How do I generate clock in Verilog ? There are many ways to generate clock in Verilog; you could use one of the following methods: Method #1 ``` 1 initial begin 2 clk = 0; 3 end 4 5 always begin 6 #5 clk = ~clk; 7 8 end ``` You could download file clock_always.v here Method #2 ``` 1 initial begin 2 clk = 0; 3 forever begin 4 #5 clk = ~clk; 5 end 6 end ``` You could download file clock_forever.v here Method #3 ``` 1 initial begin 2 clk = 0; 3 end 4 5 always begin 6 #5 clk = 0; 7 #5 clk = 1; 8 end ``` You could download file clock_always2.v here There are many ways to generate clocks: you may introduce jitter, change duty cycle. How do I test my design xyz ? To test or verify or validate any design, you need to have a test bench; writing test benches is as difficult as designing itself. Please refer to the Verilog tutorial section in "Art of Writing Test Bench" for more details. What is the difference between wire and reg ? Please refer to tidbits section for the difference between wire and reg. What is the difference between blocking and nonblocking assignment ? Please refer to tidbits section for difference between blocking and nonblocking statement. How do I write a state machine in Verilog ? Please refer to tidbits section for "writing FSM in Verilog". How do I avoid Latch in Verilog ? Latches are always bad (I don't like that statement); latches are caused when all the possible cases of assignment to variable are not covered. Well this rule applies to combinational blocks (blocks with edge sensitive lists are sequential blocks); let's look at the following example. Bad Code ``` 1 always @ (b or c) 2 begin 3 if (b) begin 4 a = c; 5 end 6 end ``` You could download file latch_bad.v here In the code above, value of a is retained, and it gets changed only when b is set to '1'. This results in a latch. (Need to phrase it right) Good Code #1 ``` 1 always @ (b or c) 2 begin 3 a = 0; 4 if (b) begin 5 a = c; 6 end 7 end ``` You could download file latch_good.v here In the code above, no matter what the value of b is, a gets value of '0' first and if b is set to '1' and c is set to '1', only then a gets '1'. This is the best way to avoid latches. Good Code #2 ``` 1 always @ (b or c) 2 begin 3 if (b) begin 4 a = c; 5 end else begin 6 a = 0; 7 end 8 end ``` You could download file latch_good2.v here In the above code, all the possible cases are covered (i.e. b = 1 and b = 0 case). How does this xyz code get synthesized ? Well it is a long story; let me cover that in the synthesis part of Verilog tutorial. You can refer to Actel HDL coding Style. One simple logic is: any code inside always blocks with edge sensitive sensitivity list, results in flip-flops and assign; inside level sensitive always blocks results in combo logic. How do I implement Memories in Verilog ? You can implement them by declaring 2-dimension arrays. More details can be found in the Verilog tutorial section "Modeling memories and FSM". How do I read and write from a file ? To Read from a file we use \$readmemh, where h stands for hex decimal. For writing we use \$writememh, \$fdisplay, \$fmonitor. You could refer to the Verilog tutorial section for more details. What is this `timescale compiler directive ? `timescale is used for specifying the reference time unit for the simulator. Syntax of the `timescale is as below: `timescale / example : `timescale 10ns/1ns Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation. Can we mix blocking and nonblocking in one always block ? Yes, we can have both blocking and nonblocking code in same always block. Some things that one should know to use this are: Blocking assignments are treated as combinational logic. One should not assign a variable in the same always block with both blocking and nonblocking assignments. Not all synthesis tools support this. (Design compiler supports this).

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