The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog HDL is a case-sensitive language. All keywords are in lowercase.

White space can contain the characters for blanks, tabs, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings.

White space characters are :

• Blank spaces
• Tabs
• Carriage returns
• New-line
• Form-feeds

Functional Equivalent Code

Bad Code : Never write code like this.

 1 module addbit(a,b,ci,sum,co);
 2 input a,b,ci;output sum co;
 3 wire a,b,ci,sum,co;endmodule

Good Code : Nice way to write code.

  1       module addbit (
  2       a,
  3       b,
  4       ci,
  5       sum,
  6       co);
  7       input           a;
  8       input           b;
  9       input           ci;
 10       output         sum;
 11       output         co;
 12       wire            a;
 13       wire            b;
 14       wire            ci;
 15       wire            sum;
 16       wire            co;
 17 
 18       endmodule

There are two forms to introduce comments.

• Single line comments begin with the token // and end with a carriage return
• Multi line comments begin with the token /* and end with the token */

  1 /* This is a
  2   Multi line comment
  3   example */
  4 module addbit (
  5 a,
  6 b,
  7 ci,
  8 sum,
  9 co);
 10 
 11 // Input Ports  Single line comment
 12 input           a;
 13 input           b;
 14 input           ci;
 15 // Output ports
 16 output         sum;
 17 output         co;
 18 // Data Types      
 19 wire            a;
 20 wire            b;
 21 wire            ci;
 22 wire            sum;
 23 wire            co; 
 24 
 25 endmodule

Verilog HDL is case sensitive

• Lower case letters are unique from upper case letters
• All Verilog keywords are lower case

 1 input                    // a Verilog Keyword
 2 wire                     // a Verilog Keyword
 3 WIRE                  // a unique name ( not a keyword)
 4 Wire                    // a unique name (not a keyword)

NOTE : Never use Verilog keywords as unique names, even if the case is different.

Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description.

• Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ )
• Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $ )
• Identifiers can be up to 1024 characters long.

data_input mu

clk_input my$clk

i386 A

Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

• Escaped identifiers begin with the back slash ( \ )
• Entire identifier is escaped by the back slash.
• Escaped identifier is terminated by white space (Characters such as commas, parentheses, and semicolons become part of the escaped identifier unless preceded by a white space)
• Terminate escaped identifiers with white space, otherwise characters that should follow the identifier are considered as part of it.

Verilog does not allow to identifier to start with a numeric character. So if you really want to use a identifier to start with a numeric value then use a escape character as shown below.

  1 // There must be white space after the
  2 // string which uses escape character
  3 module \1dff (
  4 q,      // Q output
  5 \q~ ,   // Q_out output
  6 d,      // D input
  7 cl$k,   // CLOCK input
  8 \reset* // Reset input
  9 );
 10 
 11 input d, cl$k, \reset* ;
 12 output q, \q~ ;  
 13 
 14 endmodule

You can specify constant numbers in decimal, hexadecimal, octal, or binary format. Negative numbers are represented in 2's complement form. When used in a number, the question mark (?) character is the Verilog alternative for the z character. The underscore character (_) is legal anywhere in a number except as the first character, where it is ignored.

Verilog HDL allows integer numbers to be specified as

• Sized or unsized numbers (Unsized size is 32 bits)
• In a radix of binary, octal, decimal, or hexadecimal
• Radix and hex digits (a,b,c,d,e,f) are case insensitive
• Spaces are allowed between the size, radix and value

Syntax: <size>'<radix><value>;

Verilog expands <value> filling the specified <size> by working from right-to-left

• When <size> is smaller than <value>, then leftmost bits of <value> are truncated
• When <size> is larger than <value>, then leftmost bits are filled, based on the value of the leftmost bit in <value>.
• Leftmost '0' or '1' are filled with '0'
• Leftmost 'Z' are filled with 'Z'
• Leftmost 'X' are filled with 'X'

Note : X Stands for unknown and Z stands for high impedance, 1 for logic high or 1 and 0 for logic low or 0.

• Verilog supports real constants and variables
• Verilog converts real numbers to integers by rounding
• Real Numbers can not contain 'Z' and 'X'
• Real numbers may be specified in either decimal or scientific notation
• < value >.< value >
• < mantissa >E< exponent >
• Real numbers are rounded off to the nearest integer when assigning to an integer.

Verilog Supports both types of numbers, but with certain restrictions. Like in C language we don't have int and unint types to say if a number is signed integer or unsigned integer.

Any number that does not have negative sign prefix is a positive number. Or indirect way would be "Unsigned".

Negative numbers can be specified by putting a minus sign before the size for a constant number, thus they become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic.

The example file below shows how Verilog treats signed and unsigned numbers.

  1 module signed_number;
  2 
  3 reg [31:0]  a;
  4 
  5 initial begin
  6   a = 14'h1234;
  7   $display ("Current Value of a = %h", a);
  8   a = -14'h1234;
  9   $display ("Current Value of a = %h", a);
 10   a = 32'hDEAD_BEEF;
 11   $display ("Current Value of a = %h", a);
 12   a = -32'hDEAD_BEEF;
 13   $display ("Current Value of a = %h", a);
 14    #10  $finish;
 15 end
 16 
 17 endmodule    

 Current Value of a = 00001234
 Current Value of a = ffffedcc
 Current Value of a = deadbeef
 Current Value of a = 21524111

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Deepak Kumar Tala - All rights reserved

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