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  ../images/main/bullet_green_ball.gif Introduction

Verilog PLI (Programming Language Interface) is a mechanism to invoke C or C++ functions from Verilog code.

   

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The function invoked in Verilog code is called a system call. An example of a built-in system call is $display, $stop, $random. PLI allows the user to create custom system calls, something that Verilog syntax does not allow us to do. Some of these are:-

   

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  • Power analysis.
  • Code coverage tools.
  • Modifying the Verilog simulation data structure - more accurate delays.
  • Custom output displays.
  • Co-simulation.
  • Design debug utilities.
  • Simulation analysis.
  • C-model interface to accelerate simulation.
  • Testbench modeling.

To achieve these applications of PLI, C code should have access to the internal data structure of Verilog simulator. To facilitate this Verilog PLI provides something called acc routines or simply access routines.

   

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There is a second set of routines, which are called tf routines, or simply task and function routines. The tf and acc are PLI 1.0 routines and are very vast and very old. The next set of routines, which was introduced with the latest release of Verilog 2001 is called vpi routines. These are small and crystal clear PLI routines and thus the new version PLI 2.0.

   

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You can get Verilog 2001 LRM or PLI 1.0 IEEE document for details of each and every function provided. Verilog IEEE LRMs are written in such a way that anyone with hardware background can understand. If you are unable to get hold of the above IEEE docs, then you can buy the PLI books listed in books section.

   

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  ../images/main/bulllet_4dots_orange.gif How it Works
   

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  • Write the functions in C/C++ code.
  • Compile them to generate shared libs (*.DLL in Windows and *.so in UNIX). Simulator like VCS allows static linking.
  • Use these Functions in Verilog code (Mostly Verilog Testbench).
  • Based on simulator, pass the C/C++ function details to simulator during compile process of Verilog Code (This is called linking, and you need to refer to the simulator user guide to understand how this is done).
  • Once linked just run the simulator like any other Verilog simulation.
   

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During execution of the Verilog code by the simulator, whenever the simulator encounters user defined system tasks (the ones which start with $), the execution control is passed to the PLI routine (C/C++ function).

   

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We will define a function hello, which when called will print "Hello Deepak". This example does not use any of the PLI standard functions (ACC, TF and VPI). For exact linking details, please refer to simulator manuals. Each simulator implements its own way for linking C/C++ functions to simulator.

   

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 1 #include <stdio.h> 
 2 
 3 void hello () {
 4   printf ("\nHello Deepak\n");
 5 }
You could download file hello.c here
   

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 1 module hello_pli ();
 2   	 
 3 initial begin
 4   $hello;
 5    #10  $finish;
 6 end
 7   	  
 8 endmodule
You could download file hello_pli.v here
   

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  ../images/main/bullet_star_pink.gif Running the Simulation

Once linking is done, simulation is run as a normal simulation as we saw earlier, with slight modification to the command line options: we need to tell the simulator that we are using PLI (Modelsim needs to know which shared objects to load in the command line).

   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com