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Combinational Section
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This section can be modeled using functions, assign statements or using always blocks with a case statement. For the time being let's see the always block version |
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1 always @ (state or req_0 or req_1 or req_2 or req_3)
2 begin
3 next_state = 0;
4 case(state)
5 IDLE : if (req_0 == 1'b1) begin
6 next_state = GNT0;
7 end else if (req_1 == 1'b1) begin
8 next_state= GNT1;
9 end else if (req_2 == 1'b1) begin
10 next_state= GNT2;
11 end else if (req_3 == 1'b1) begin
12 next_state= GNT3;
13 end else begin
14 next_state = IDLE;
15 end
16 GNT0 : if (req_0 == 1'b0) begin
17 next_state = IDLE;
18 end else begin
19 next_state = GNT0;
20 end
21 GNT1 : if (req_1 == 1'b0) begin
22 next_state = IDLE;
23 end else begin
24 next_state = GNT1;
25 end
26 GNT2 : if (req_2 == 1'b0) begin
27 next_state = IDLE;
28 end else begin
29 next_state = GNT2;
30 end
31 GNT3 : if (req_3 == 1'b0) begin
32 next_state = IDLE;
33 end else begin
34 next_state = GNT3;
35 end
36 default : next_state = IDLE;
37 endcase
38 end
You could download file fsm_combo.v here
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Sequential Section
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This section has to be modeled using only edge sensitive logic such as always block with posedge or negedge of clock. |
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1 always @ (posedge clock)
2 begin : OUTPUT_LOGIC
3 if (reset == 1'b1) begin
4 gnt_0 <= #1 1'b0;
5 gnt_1 <= #1 1'b0;
6 gnt_2 <= #1 1'b0;
7 gnt_3 <= #1 1'b0;
8 state <= #1 IDLE;
9 end else begin
10 state <= #1 next_state;
11 case(state)
12 IDLE : begin
13 gnt_0 <= #1 1'b0;
14 gnt_1 <= #1 1'b0;
15 gnt_2 <= #1 1'b0;
16 gnt_3 <= #1 1'b0;
17 end
18 GNT0 : begin
19 gnt_0 <= #1 1'b1;
20 end
21 GNT1 : begin
22 gnt_1 <= #1 1'b1;
23 end
24 GNT2 : begin
25 gnt_2 <= #1 1'b1;
26 end
27 GNT3 : begin
28 gnt_3 <= #1 1'b1;
29 end
30 default : begin
31 state <= #1 IDLE;
32 end
33 endcase
34 end
35 end
You could download file fsm_seq.v here
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Full Code using binary encoding
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1 module fsm_full(
2 clock , // Clock
3 reset , // Active high reset
4 req_0 , // Active high request from agent 0
5 req_1 , // Active high request from agent 1
6 req_2 , // Active high request from agent 2
7 req_3 , // Active high request from agent 3
8 gnt_0 , // Active high grant to agent 0
9 gnt_1 , // Active high grant to agent 1
10 gnt_2 , // Active high grant to agent 2
11 gnt_3 // Active high grant to agent 3
12 );
13 // Port declaration here
14 input clock ; // Clock
15 input reset ; // Active high reset
16 input req_0 ; // Active high request from agent 0
17 input req_1 ; // Active high request from agent 1
18 input req_2 ; // Active high request from agent 2
19 input req_3 ; // Active high request from agent 3
20 output gnt_0 ; // Active high grant to agent 0
21 output gnt_1 ; // Active high grant to agent 1
22 output gnt_2 ; // Active high grant to agent 2
23 output gnt_3 ; // Active high grant to agent
24
25 // Internal Variables
26 reg gnt_0 ; // Active high grant to agent 0
27 reg gnt_1 ; // Active high grant to agent 1
28 reg gnt_2 ; // Active high grant to agent 2
29 reg gnt_3 ; // Active high grant to agent
30
31 parameter [2:0] IDLE = 3'b000;
32 parameter [2:0] GNT0 = 3'b001;
33 parameter [2:0] GNT1 = 3'b010;
34 parameter [2:0] GNT2 = 3'b011;
35 parameter [2:0] GNT3 = 3'b100;
36
37 reg [2:0] state, next_state;
38
39 always @ (state or req_0 or req_1 or req_2 or req_3)
40 begin
41 next_state = 0;
42 case(state)
43 IDLE : if (req_0 == 1'b1) begin
44 next_state = GNT0;
45 end else if (req_1 == 1'b1) begin
46 next_state= GNT1;
47 end else if (req_2 == 1'b1) begin
48 next_state= GNT2;
49 end else if (req_3 == 1'b1) begin
50 next_state= GNT3;
51 end else begin
52 next_state = IDLE;
53 end
54 GNT0 : if (req_0 == 1'b0) begin
55 next_state = IDLE;
56 end else begin
57 next_state = GNT0;
58 end
59 GNT1 : if (req_1 == 1'b0) begin
60 next_state = IDLE;
61 end else begin
62 next_state = GNT1;
63 end
64 GNT2 : if (req_2 == 1'b0) begin
65 next_state = IDLE;
66 end else begin
67 next_state = GNT2;
68 end
69 GNT3 : if (req_3 == 1'b0) begin
70 next_state = IDLE;
71 end else begin
72 next_state = GNT3;
73 end
74 default : next_state = IDLE;
75 endcase
76 end
77
78 always @ (posedge clock)
79 begin : OUTPUT_LOGIC
80 if (reset) begin
81 gnt_0 <= #1 1'b0;
82 gnt_1 <= #1 1'b0;
83 gnt_2 <= #1 1'b0;
84 gnt_3 <= #1 1'b0;
85 state <= #1 IDLE;
86 end else begin
87 state <= #1 next_state;
88 case(state)
89 IDLE : begin
90 gnt_0 <= #1 1'b0;
91 gnt_1 <= #1 1'b0;
92 gnt_2 <= #1 1'b0;
93 gnt_3 <= #1 1'b0;
94 end
95 GNT0 : begin
96 gnt_0 <= #1 1'b1;
97 end
98 GNT1 : begin
99 gnt_1 <= #1 1'b1;
100 end
101 GNT2 : begin
102 gnt_2 <= #1 1'b1;
103 end
104 GNT3 : begin
105 gnt_3 <= #1 1'b1;
106 end
107 default : begin
108 state <= #1 IDLE;
109 end
110 endcase
111 end
112 end
113
114 endmodule
You could download file fsm_full.v here
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Testbench |
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1 `include "fsm_full.v"
2
3 module fsm_full_tb();
4 reg clock , reset ;
5 reg req_0 , req_1 , req_2 , req_3;
6 wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
7
8 initial begin
9 $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3");
10 $monitor("%g\t %b %b %b %b %b %b %b %b",
11 $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
12 clock = 0;
13 reset = 0;
14 req_0 = 0;
15 req_1 = 0;
16 req_2 = 0;
17 req_3 = 0;
18 #10 reset = 1;
19 #10 reset = 0;
20 #10 req_0 = 1;
21 #20 req_0 = 0;
22 #10 req_1 = 1;
23 #20 req_1 = 0;
24 #10 req_2 = 1;
25 #20 req_2 = 0;
26 #10 req_3 = 1;
27 #20 req_3 = 0;
28 #10 $finish;
29 end
30
31 always
32 #2 clock = ~clock;
33
34
35 fsm_full U_fsm_full(
36 clock , // Clock
37 reset , // Active high reset
38 req_0 , // Active high request from agent 0
39 req_1 , // Active high request from agent 1
40 req_2 , // Active high request from agent 2
41 req_3 , // Active high request from agent 3
42 gnt_0 , // Active high grant to agent 0
43 gnt_1 , // Active high grant to agent 1
44 gnt_2 , // Active high grant to agent 2
45 gnt_3 // Active high grant to agent 3
46 );
47
48
49
50 endmodule
You could download file fsm_full_tb.v here
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Simulator Output |
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Time R0 R1 R2 R3 G0 G1 G2 G3
0 0 0 0 0 x x x x
7 0 0 0 0 0 0 0 0
30 1 0 0 0 0 0 0 0
35 1 0 0 0 1 0 0 0
50 0 0 0 0 1 0 0 0
55 0 0 0 0 0 0 0 0
60 0 1 0 0 0 0 0 0
67 0 1 0 0 0 1 0 0
80 0 0 0 0 0 1 0 0
87 0 0 0 0 0 0 0 0
90 0 0 1 0 0 0 0 0
95 0 0 1 0 0 0 1 0
110 0 0 0 0 0 0 1 0
115 0 0 0 0 0 0 0 0
120 0 0 0 1 0 0 0 0
127 0 0 0 1 0 0 0 1
140 0 0 0 0 0 0 0 1
147 0 0 0 0 0 0 0 0
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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