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  ../images/main/bullet_green_ball.gif Writing a TestBench

First step of any testbench creation is building a dummy template which basically declares inputs to DUT as reg and outputs from DUT as wire, then instantiates the DUT as shown in the code below. Note that there is no port list for the test bench.

   

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  ../images/main/bulllet_4dots_orange.gif Test Bench
   

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  1 module counter_tb;
  2   reg clk, reset, enable; 
  3   wire [3:0] count; 
  4     
  5   counter U0 ( 
  6   .clk    (clk), 
  7   .reset  (reset), 
  8   .enable (enable), 
  9   .count  (count) 
 10   ); 
 11     
 12 endmodule 
You could download file counter_tb1.v here
   

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Next step would be to add clock generator logic: this is straight forward, as we know how to generate a clock. Before we add a clock generator we need to drive all the inputs to DUT to some known state as shown in the code below.

   

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  ../images/main/bulllet_4dots_orange.gif Test Bench with Clock generator
   

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  1 module counter_tb; 
  2   reg clk, reset, enable; 
  3   wire [3:0] count; 
  4     
  5   counter U0 ( 
  6   .clk    (clk), 
  7   .reset  (reset), 
  8   .enable (enable), 
  9   .count  (count) 
 10   ); 
 11     
 12   initial 
 13   begin 
 14     clk = 0; 
 15     reset = 0; 
 16     enable = 0; 
 17   end 
 18     
 19   always 
 20      #5  clk =  ! clk; 
 21     
 22 endmodule 
You could download file counter_tb2.v here
   

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An initial block in Verilog is executed only once, thus simulator sets the value of clk, reset and enable to 0; by looking at the counter code (of course you will be referring to the DUT specs) could be found that driving 0 makes all these signals disabled.

   

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There are many ways to generate a clock: one could use a forever loop inside an initial block as an alternative to the above code. You could a add parameter or use `define to control the clock frequency. You may write a complex clock generator, where we could introduce PPM (Parts per million, clock width drift), then control the duty cycle. All the above depends on the specs of the DUT and the creativity of a "Test Bench Designer".

   

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At this point, you would like to test if the testbench is generating the clock correctly: well you can compile it with any Verilog simulator. You need to give command line options as shown below.

   

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C:\www.asic-world.com\veridos counter.v counter_tb.v

   

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Of course it is a very good idea to keep file names the same as the module name. Ok, coming back to compiling, you will see that the simulator does print anything on screen, or dump any waveform. Thus we need to add support for all the above as shown in the code below.

   

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  ../images/main/bulllet_4dots_orange.gif Test Bench continues...
   

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  1 module counter_tb; 
  2   reg clk, reset, enable; 
  3   wire [3:0] count; 
  4     
  5   counter U0 ( 
  6   .clk    (clk), 
  7   .reset  (reset), 
  8   .enable (enable), 
  9   .count  (count) 
 10   ); 
 11     
 12   initial begin
 13     clk = 0; 
 14     reset = 0; 
 15     enable = 0; 
 16   end 
 17     
 18   always  
 19      #5  clk =  ! clk; 
 20     
 21   initial  begin
 22     $dumpfile ("counter.vcd"); 
 23     $dumpvars; 
 24   end 
 25     
 26   initial  begin
 27     $display("\t\ttime,\tclk,\treset,\tenable,\tcount"); 
 28     $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count); 
 29   end 
 30     
 31   initial 
 32    #100  $finish; 
 33     
 34   //Rest of testbench code after this line 
 35     
 36 endmodule
You could download file counter_tb3.v here
   

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$dumpfile is used for specifying the file that the simulator will use to store the waveform, that can be used later using a waveform viewer. (Please refer to the tools section for freeware versions of viewers.) $dumpvars basically instructs the Verilog compiler to start dumping all the signals to "counter.vcd".

   

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$display is used for printing text or variables to stdout (screen), \t is for inserting tabs. The syntax is the same as for printf C language. $monitor in the second line is a bit different: $monitor keeps track of changes to the variables that are in the list (clk, reset, enable, count). Whenever any of them changes, it prints their value, in the respective radix specified.

   

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$finish is used for terminating the simulation after #100 time units (note: all the initial, always blocks start execution at time 0).

   

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Now that we have written the basic skeleton, let's compile and see what we have just coded. Output of the simulator is shown below.

   

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 C:\www.asic-world.com>veridos counter.v counter_tb.v
 VeriWell for Win32 HDL Version 2.1.4 Fri Jan 17 21:33:25 2003
 
 This is a free version of the VeriWell for Win32 Simulator
 Distribute this freely; call 1-800-VERIWELL for ordering information
 See the file "!readme.1st" for more information
 
 Copyright (c) 1993-97 Wellspring Solutions, Inc.
 All rights reserved
 
 
 Memory Available: 0
 Entering Phase I...
 Compiling source file : counter.v
 Compiling source file : counter_tb.v
 The size of this model is [2%, 5%] of the capacity of the free version
 
 Entering Phase II...
 Entering Phase III...
 No errors in compilation
 Top-level modules:
 counter_tb
 
     time 	clk, 	reset, 	enable, count
     0, 		0, 	0, 	0, 	x
     5, 		1, 	0, 	0, 	x
     10, 	0, 	0, 	0, 	x
     15, 	1, 	0, 	0, 	x
     20, 	0, 	0, 	0, 	x
     25, 	1, 	0, 	0, 	x
     30, 	0, 	0, 	0, 	x
     35, 	1, 	0, 	0, 	x
     40, 	0, 	0, 	0, 	x
     45, 	1, 	0, 	0, 	x
     50, 	0, 	0, 	0, 	x
     55, 	1, 	0, 	0, 	x
     60, 	0, 	0, 	0, 	x
     65, 	1, 	0, 	0, 	x
     70, 	0, 	0, 	0, 	x
     75, 	1, 	0, 	0, 	x
     80, 	0, 	0, 	0, 	x
     85, 	1, 	0, 	0, 	x
     90, 	0, 	0, 	0, 	x
     95, 	1, 	0, 	0, 	x
 
 Exiting VeriWell for Win32 at time 100
 0 Errors, 0 Warnings, Memory Used: 0
 Compile time = 0.0 Load time = 0.0 Simulation time = 0.1
 
 Normal exit
 Thank you for using VeriWell for Win32
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com