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Reserved Names
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Vera has a set of keywords. These are listed below , and must not be used as identifiers. In addition, Vera uses a set of names that start with VERA, Vera, or vera. Therefore, using those names as a prefix for identifiers should be avoided. |
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Keywords
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Keywords
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Keywords
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Keywords
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after
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coverage_group
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join
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reg
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all
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coverage_option
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little_endian
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repeat
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any
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coverage_val
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local
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return
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around
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default
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m_bad_state
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rules
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assoc_index
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depth
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m_bad_trans
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shadow
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assoc_size
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dist
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m_state
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soft
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async
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do
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m_trans
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state
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bad_state
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else
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negedge
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static
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bad_trans
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end
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new
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string
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before
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enum
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newcov
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super
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begin
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event
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non_rand
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task
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big_endian
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export
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none
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terminate
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bind
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extends
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not
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this
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bind_var
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extern
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null
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trans
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bit
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for
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or
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typedef
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bit_normal
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foreach
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output
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unpacked
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bit_reverse
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fork
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packed
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var
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break
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function
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port
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vca
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breakpoint
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hdl_node
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posedge
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vector
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case
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hdl_task
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proceed
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verilog_node
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casex
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hide
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prod
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verilog_task
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casez
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if
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prodget
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vhdl_node
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class
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illegal_self_transition
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prodset
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vhdl_task
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CLOCK
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illegal_state
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program
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virtual
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constraint
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illegal_transition
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protected
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virtuals
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continue
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in
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public
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void
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coverage_block
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inout
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rand
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while
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coverage_def
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input
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randc
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wildcard
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coverage_depth
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integer
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randcase
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with
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coverage_goal
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interface
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randseq
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There are predefined methods and class names. For details refer to Vera/OpenVera reference manual. |
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Strings Constants
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A string constant is a sequence of characters enclosed by double quotes. A string constant must be contained in a single line unless the new line is immediately preceded by a back slash. In this case, the back slash and new line are ignored.There is no maximum size limit for string constants. |
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Example : Strings Constants
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1 program string_constants {
2 string s = "This is string constant";
3 printf("String Assigned :%s\n",s);
4 }
You could download file string_constants.vr here
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Numbers
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Vera supports two format of representing numbers. |
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- A simple decimal integer can be specified as a sequence of digits from 0 to 9. The negative sign is for specifying negative integers. Underscores are ignored.
- size ´base number : This is same as in Verilog.
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size ´base number |
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- size : Specifies the number of bits in the number. If the size is omitted, the number of bits for number defaults to the host machine word size. A plus or minus sign before the size specification signifies the number¿s polarity. The maximum size is 65535. A size of 0 results in a compilation failure.
- base : Is always preceded by a single quote (´). The base can be one of the following: d(ecimal), h(exadecimal), o(ctal), or b(inary). The base identifier can be either upper or lower case.
- number : - The valid elements of number for each base.
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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