Transaction-level modeling is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of the functional units or of the communication architecture. Communication mechanisms such as busses or FIFOs are modeled as channels, and are presented to modules using SystemC interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange.

Transaction-level modeling also enables higher simulation speed than pin-based interfaces. Transaction-level models can be used anytime their increased level of abstraction is beneficial.

Transaction level modeling (TLM) is put forward as a promising solution above Register Transfer Level (RTL) in the SoC design flow.

Transcation level modeling motivated due to following reasons also.

• Providing an early platform for software development.
• System Level Design Exploration and Verification.
• The need to use System Level Models in Block Level Verification.

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