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Introduction
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The SystemC Class Library has been developed to support system level design. It runs on both PC and UNIX platforms, and is freely downloadable from the web. |
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The class library is being released in stages. The first stage, release 1.0 (presently at version 1.0.2) provides all the necessary modelling facilities to describe systems similar to those which can be described using a hardware description language, such as VHDL. Version 1.0 provides a simulation kernel, data types appropriate for fixed point arithmetic, communication channels which behave like pieces of wire (signals), and modules to break down a design into smaller parts. |
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In Release 2.0 (presently at version 2.0.1), the class library has been extensively re-written to provide an upgrade path into true system level design. Features that were built-in to version 1.0, such as signals, are now built upon an underlying structure of channels, interfaces, and ports. Events have been provided as a primitive means of triggering behaviour, together with a set of primitive channels such as FIFO and mutex. Version 2.0 allows much more powerful modelling to be achieved by modelling at the level of transactions. |
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In future, Version 3.0 of the class library will be extended to cover modelling of operating systems, to support the development of models of embedded software. |
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It is also possible to provide additional libraries to support a particular design methodology. Examples of this are the Master-Slave Communication Library, and the SystemC Verification Library (SCV). |
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The SystemC Class Library has been developed by a group of companies forming the Open SystemC Initiative (OSCI). For more information, and to download the freely available source code |
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You could download file d_ff.cpp here
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One can describe a simple Flip flop as that in above figure as well as one can describe a complicated designs. SystemC is one of the languages available in the industry for modelling the Hardware. SystemC allows us to design a Digital design at very high level. SystemC allows hardware designers to express their designs with behavioral constructs, deterring the details of implementation to a later stage of design in the final design. With addition of SystemC Verification, same lanugage can be used for design and also for verification. |
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Many engineers who want to learn SystemC, most often ask this question, how much time it will take to learn SystemC?, Well my answer to them is "It may not take more then one week, if you happen to know at least one programming language and a bit about OOPS". |
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