SystemVerilog DPI is much more easy to interface with external C like languages. We can still use the exisiting TF and ACC routines. Below is same example shown with VPI. There are only three files that are different

• counter_dpi.c
• counter.sv
• Makefile

  1 #include <stdio.h>
  2 #include <stdlib.h>
  3 #include "acc_user.h"
  4 #include "vcs_acc_user.h"
  5 #include "svdpi.h"
  6 
  7 
  8 #include "counter_tb_ports.h"
  9 #include "counter_tb_exports.h"
 10 
 11 void sc_counter_init() {
 12   init_sc();  // Initialize SystemC Model
 13 }
 14 
 15 int sc_counter_interface(int iclk, int idout) {
 16   static unsigned long SimNow = 0;
 17   int lrst;
 18   // IO ports systemC testbench
 19   static INVECTOR   invector;
 20   static OUTVECTOR  outvector;
 21   invector.clk   = iclk;
 22   invector.d_out = idout;
 23   // Execute the SytemC Shell
 24   exec_sc(&invector, &outvector, (tf_gettime()-SimNow));
 25   SimNow = tf_gettime();
 26   lrst =  outvector.rst;
 27   if (outvector.done) {
 28     tf_dofinish();
 29   }
 30 
 31   return(lrst);
 32 }

  1 `timescale 1ns / 1ns
  2 //---------------------------------------
  3 // Verilog DUT 
  4 //---------------------------------------
  5 module counter(
  6 rst,   // Reset input
  7 clk,   // Clock Input
  8 d_out  // Counter output
  9 );
 10 // Port Declation
 11 input      rst;
 12 input      clk;
 13 output  [31:0]  d_out;
 14 // Internal data type
 15 reg  [31:0]  d_out;
 16 // Code starts here
 17 always @ (posedge clk)
 18   if (rst) d_out = 0;
 19   else d_out = d_out + 1;
 20 
 21 endmodule
 22 //---------------------------------------
 23 // Testbench top level
 24 //---------------------------------------
 25 module tb();
 26 reg      rst;
 27 reg      clk;
 28 integer  iclk,irst,idout;
 29 wire  [31:0]  d_out;
 30 // Import the C functions
 31 import "DPI" function void sc_counter_init();
 32 import "DPI" function int sc_counter_interface
 33     (input int iclk, idout);
 34 // Assign Integer to reg
 35 always @ (clk)   iclk  =  clk;
 36 always @ (irst)  rst   =  irst;
 37 always @ (d_out) idout =  d_out;
 38 // Call SystemC interface method, when ever
 39 // Input changes
 40 always @ (idout or iclk)
 41 begin
 42   irst = sc_counter_interface(iclk,idout);
 43 end
 44 // Init the simulation
 45 initial begin
 46  sc_counter_init();
 47  clk = 0;
 48 end
 49 // Clock generator
 50 always #1 clk = ~clk;
 51 // DUT connection
 52 counter dut (
 53     // Inputs
 54     rst,
 55     clk,
 56     // Outputs
 57     d_out
 58 );
 59 
 60 endmodule

  1 # Point to you systemC Install Dir
  2 INC_OPT      = -I. -I$(VCS_HOME)/include \
  3 	       -I$(SYSTEMC_HOME)/include
  4 COMP_OPT     = -c 
  5 LIB_OPT      = $(SYSTEMC_HOME)/lib-linux/libsystemc.a
  6 CPP_FILE     = counter.cpp counter_tb.cpp 
  7 DPI_C_FILE   = counter_dpi.c
  8 V_FILE       = counter.sv
  9 
 10 DPI_O_FILE   = counter.o counter_dpi.o counter_tb.o
 11 VCS_OPT      = -CFLAGS -lstdc++ $(LIB_OPT)
 12 
 13 dpi:c cpp
 14 	vcs -sverilog $(DPI_O_FILE) counter.sv $(VCS_OPT) -R
 15 
 16 cpp : $(CPP_FILE)
 17 	gcc $(INC_OPT) $(COMP_OPT) $(CPP_FILE)
 18 
 19 c : $(DPI_C_FILE)
 20 	gcc $(INC_OPT) $(COMP_OPT) $(DPI_C_FILE)
 21 
 22 clean:
 23 	rm -rf *.o simv csrc simv.daidir vcs.key *.vpd *.vcd \
 24 	vc_hdrs.h

  1 Note: VCD trace timescale unit is set by user to 1e-9 sec.
  2 @0 s Started SystemC Schedular
  3 @0 s Asserting Reset 
  4 @2 nsCounter Monitor : tb 0 dut 0
  5 @4 nsCounter Monitor : tb 0 dut 0
  6 @6 nsCounter Monitor : tb 0 dut 0
  7 @8 nsCounter Monitor : tb 0 dut 0
  8 @10 nsCounter Monitor : tb 0 dut 0
  9 @12 nsCounter Monitor : tb 0 dut 0
 10 @14 nsCounter Monitor : tb 0 dut 0
 11 @16 nsCounter Monitor : tb 0 dut 0
 12 @18 nsCounter Monitor : tb 0 dut 0
 13 @20 ns De-asserting Reset 
 14 @20 nsCounter Monitor : tb 0 dut 0
 15 @22 nsCounter Monitor : tb 1 dut 1
 16 @24 nsCounter Monitor : tb 2 dut 2
 17 @26 nsCounter Monitor : tb 3 dut 3
 18 @28 nsCounter Monitor : tb 4 dut 4
 19 @30 nsCounter Monitor : tb 5 dut 5
 20 @32 nsCounter Monitor : tb 6 dut 6
 21 @34 nsCounter Monitor : tb 7 dut 7
 22 @36 nsCounter Monitor : tb 8 dut 8
 23 @38 nsCounter Monitor : tb 9 dut 9
 24 @40 nsCounter Monitor : tb 10 dut 10
 25 @42 nsCounter Monitor : tb 11 dut 11
 26 @44 nsCounter Monitor : tb 12 dut 12
 27 @46 nsCounter Monitor : tb 13 dut 13
 28 @48 nsCounter Monitor : tb 14 dut 14
 29 @50 nsCounter Monitor : tb 15 dut 15
 30 @52 nsCounter Monitor : tb 16 dut 16
 31 @54 nsCounter Monitor : tb 17 dut 17
 32 @56 nsCounter Monitor : tb 18 dut 18
 33 @58 nsCounter Monitor : tb 19 dut 19
 34 =======================================
 35  SIMULATION PASSED
 36 =======================================
 37 @60 nsCounter Monitor : tb 20 dut 20

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Deepak Kumar Tala - All rights reserved

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