Interface With Simulators

Interfacing with simulator

Compiling e Files

Linking Specman Elite with Simulators

	Interfacing with VCS
	Interfacing with NCVerilog
	Interfacing with Modelsim

Simulation-related constructs

simulator_command()

Verilog Statements

	Verilog Code
	Verilog Function
	Verilog Task
	Verilog Import
	Verilog Time
	Verilog variable reg \| wire
	Verilog variable memory

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Deepak Kumar Tala - All rights reserved

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