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  ../../images/main/bullet_green_ball.gif Synchronous FIFO
   

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   1 -------------------------------------------------------
   2 -- Design Name : syn_fifo
   3 -- File Name   : syn_fifo.vhd
   4 -- Function    : Synchronous (single clock) FIFO
   5 -- Coder       : Deepak Kumar Tala (Verilog)
   6 -- Translator  : Alexander H Pham (VHDL)
   7 -------------------------------------------------------
   8 library ieee;
   9     use ieee.std_logic_1164.all;
  10     use ieee.std_logic_unsigned.all;
  11 
  12 entity syn_fifo is
  13     generic (
  14         DATA_WIDTH :integer := 8;
  15         ADDR_WIDTH :integer := 8
  16     );
  17     port (
  18         clk      :in  std_logic;-- Clock input
  19         rst      :in  std_logic;-- Active high reset
  20         wr_cs    :in  std_logic;-- Write chip select
  21         rd_cs    :in  std_logic;-- Read chipe select
  22         data_in  :in  std_logic_vector (DATA_WIDTH-1 downto 0);-- Data input
  23         rd_en    :in  std_logic;-- Read enable
  24         wr_en    :in  std_logic;-- Write Enable
  25         data_out :out std_logic_vector (DATA_WIDTH-1 downto 0);-- Data Output
  26         empty    :out std_logic;-- FIFO empty
  27         full     :out std_logic -- FIFO full
  28     );
  29 end entity;
  30 architecture rtl of syn_fifo is
  31    -------------Internal variables-------------------
  32     constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
  33 
  34     signal wr_pointer   :std_logic_vector (ADDR_WIDTH-1 downto 0);
  35     signal rd_pointer   :std_logic_vector (ADDR_WIDTH-1 downto 0);
  36     signal status_cnt   :std_logic_vector (ADDR_WIDTH   downto 0);
  37     signal data_ram_in  :std_logic_vector (DATA_WIDTH-1 downto 0);
  38     signal data_ram_out :std_logic_vector (DATA_WIDTH-1 downto 0);
  39     
  40     component ram_dp_ar_aw is
  41     generic (
  42         DATA_WIDTH :integer := 8;
  43         ADDR_WIDTH :integer := 8
  44     );
  45     port (
  46         address_0 :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_0 Input
  47         data_0    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_0 bi-directional
  48         cs_0      :in    std_logic;                                -- Chip Select
  49         we_0      :in    std_logic;                                -- Write Enable/Read Enable
  50         oe_0      :in    std_logic;                                -- Output Enable
  51         address_1 :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_1 Input
  52         data_1    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_1 bi-directional
  53         cs_1      :in    std_logic;                                -- Chip Select
  54         we_1      :in    std_logic;                                -- Write Enable/Read Enable
  55         oe_1      :in    std_logic                                 -- Output Enable
  56     );
  57     end component;
  58     
  59 begin
  60    -------------Code Start---------------------------
  61     full  <= '1' when (status_cnt = (RAM_DEPTH-1)) else '0';
  62     empty <= '1' when (status_cnt = 0) else '0';
  63 
  64     WRITE_POINTER:
  65     process (clk, rst) begin
  66         if (rst = '1') then
  67             wr_pointer <= (others=>'0');
  68         elsif (rising_edge(clk)) then
  69             if (wr_cs = '1' and wr_en = '1') then
  70                 wr_pointer <= wr_pointer + 1;
  71             end if;
  72         end if;
  73     end process;
  74     
  75     READ_POINTER:
  76     process (clk, rst) begin
  77         if (rst  = '1') then
  78             rd_pointer <= (others=>'0');
  79         elsif (rising_edge(clk)) then
  80             if (rd_cs = '1' and rd_en = '1') then
  81                 rd_pointer <= rd_pointer + 1;
  82             end if;
  83         end if;
  84     end process;
  85 
  86     READ_DATA:
  87     process (clk, rst) begin
  88         if (rst = '1') then
  89             data_out <= (others=>'0');
  90         elsif (rising_edge(clk)) then
  91             if (rd_cs = '1' and rd_en = '1') then
  92                 data_out <= data_ram_out;
  93             end if;
  94         end if;
  95     end process;
  96 
  97     STATUS_COUNTER:
  98     process (clk, rst) begin
  99         if (rst = '1') then
 100             status_cnt <= (others=>'0');
 101        -- Read but no write.
 102         elsif (rising_edge(clk)) then
 103             if ((rd_cs = '1' and rd_en = '1') and not(wr_cs = '1' and wr_en = '1') and (status_cnt /= 0)) then
 104                 status_cnt <= status_cnt - 1;
 105            -- Write but no read.
 106             elsif ((wr_cs = '1' and wr_en = '1') and not (rd_cs = '1' and rd_en = '1') and (status_cnt /= RAM_DEPTH)) then
 107                 status_cnt <= status_cnt + 1;
 108             end if;
 109         end if;
 110     end process;
 111     
 112     data_ram_in <= data_in;
 113 
 114     DP_RAM : ram_dp_ar_aw
 115     generic map (
 116         DATA_WIDTH => DATA_WIDTH,
 117         ADDR_WIDTH => ADDR_WIDTH
 118     )
 119     port map (
 120         address_0 => wr_pointer,   -- address_0 input
 121         data_0    => data_ram_in,  -- data_0 bi-directional
 122         cs_0      => wr_cs,        -- chip select
 123         we_0      => wr_en,        -- write enable
 124         oe_0      => '0',          -- output enable
 125         address_1 => rd_pointer,   -- address_q input
 126         data_1    => data_ram_out, -- data_1 bi-directional
 127         cs_1      => rd_cs,        -- chip select
 128         we_1      => '0',          -- Read enable
 129         oe_1      => rd_en         -- output enable
 130     );
 131     
 132 end architecture;
You could download file vhdl_examples here
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com