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  ../../images/main/bullet_green_ball.gif LFSR Package
   

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  1 -------------------------------------------------------
  2 -- Design Name : User Pakage
  3 -- File Name   : lfsr_pkg.vhd
  4 -- Function    : Defines function for LFSR
  5 -- Coder       : Alexander H Pham (VHDL)
  6 -------------------------------------------------------
  7 library ieee;
  8     use ieee.std_logic_1164.all;
  9     use ieee.std_logic_unsigned.all;
 10     
 11 package lfsr_pkg is
 12 
 13    -- LFSR Feedback for 2**n
 14     function many_to_one_fb (DATA, TAPS :std_logic_vector) return std_logic_vector;
 15     function one_to_many_fb (DATA, TAPS :std_logic_vector) return std_logic_vector;
 16 
 17 end;
 18 
 19 package body lfsr_pkg is
 20 
 21     function many_to_one_fb (DATA, TAPS :std_logic_vector) return std_logic_vector is
 22         variable xor_taps :std_logic;
 23         variable all_0s   :std_logic;
 24         variable feedback :std_logic;
 25     begin
 26 
 27        -- Validate if lfsr = to zero (Prohibit Value)
 28         if (DATA(DATA'length-2 downto 0) = 0) then
 29             all_0s := '1';
 30         else
 31             all_0s := '0';
 32         end if;
 33 
 34         xor_taps := '0';
 35         for idx in 0 to (TAPS'length-1) loop
 36             if (TAPS(idx) = '1') then
 37                 xor_taps := xor_taps xor DATA(idx);
 38             end if;
 39         end loop;
 40 
 41         feedback := xor_taps xor all_0s;
 42 
 43         return DATA((DATA'length-2) downto 0) & feedback;
 44 
 45     end function;
 46 
 47     function one_to_many_fb (DATA, TAPS :std_logic_vector) return std_logic_vector is
 48         variable xor_taps  :std_logic;
 49         variable all_0s    :std_logic;
 50         variable feedback  :std_logic;
 51         variable result    :std_logic_vector (DATA'length-1 downto 0);
 52     begin
 53 
 54        -- Validate if lfsr = to zero (Prohibit Value)
 55         if (DATA(DATA'length-2 downto 0) = 0) then
 56             all_0s := '1';
 57         else
 58             all_0s := '0';
 59         end if;
 60 
 61         feedback := DATA(DATA'length-1) xor all_0s;
 62 
 63        -- XOR the taps with the feedback
 64         result(0) := feedback;
 65         for idx in 0 to (TAPS'length-2) loop
 66             if (TAPS(idx) = '1') then
 67                 result(idx+1) := feedback xor DATA(idx);
 68             else
 69                 result(idx+1) := DATA(idx);
 70             end if;
 71         end loop;
 72         
 73         return result;
 74 
 75     end function;
 76 end package body;
 77 
 78 
 79     
You could download file vhdl_examples here
   

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Package Implementation

   

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  1 -------------------------------------------------------
  2 -- Design Name : lfsr_implement
  3 -- File Name   : lfsr_implement.vhd
  4 -- Function    : Use of the lfsr package
  5 -- Coder       : Alexander H Pham (VHDL)
  6 -------------------------------------------------------
  7 library ieee;
  8     use ieee.std_logic_1164.all;
  9     use work.lfsr_pkg.all;
 10 
 11 entity lfsr_implement is
 12     port (
 13         clk    :in  std_logic;
 14         rst    :in  std_logic;
 15         lfsr_1 :out std_logic_vector (7 downto 0);
 16         lfsr_2 :out std_logic_vector (7 downto 0)
 17     );
 18 end entity;
 19 
 20 architecture rtl of lfsr_implement is
 21     constant taps   :std_logic_vector (7 downto 0) := "10001110";
 22     signal   lfsr_a :std_logic_vector (7 downto 0);
 23     signal   lfsr_b :std_logic_vector (7 downto 0);
 24 
 25 begin
 26 
 27     process (clk, rst) begin
 28         if (rst = '1') then
 29             lfsr_a <=  (others=>'0');
 30             lfsr_b <=  (others=>'0');
 31         elsif (rising_edge(clk)) then
 32             lfsr_a <= many_to_one_fb (lfsr_a, taps);
 33             lfsr_b <= one_to_many_fb (lfsr_b, taps);
 34         end if;
 35     end process;
 36 
 37     lfsr_1 <= lfsr_a;
 38     lfsr_2 <= lfsr_b;
 39 end architecture;
 40 
 41 ------------------------------------------------------------------------------
 42 --  TEST BENCH
 43 ------------------------------------------------------------------------------
 44 library ieee;
 45     use ieee.std_logic_1164.all;
 46     use ieee.std_logic_unsigned.all;
 47     use ieee.std_logic_textio.all;
 48     use std.textio.all;
 49 
 50 entity lfsr_tb is
 51 end entity;
 52 architecture test of lfsr_tb is
 53 
 54     signal clk    :std_logic := '0';
 55     signal rst    :std_logic := '1';
 56     signal lfsr_1 :std_logic_vector (7 downto 0);
 57     signal lfsr_2 :std_logic_vector (7 downto 0);
 58     
 59     component lfsr_implement is
 60     port (
 61         clk    :in  std_logic;
 62         rst    :in  std_logic;
 63         lfsr_1 :out std_logic_vector (7 downto 0);
 64         lfsr_2 :out std_logic_vector (7 downto 0)
 65     );
 66     end component;
 67 begin
 68 
 69    -- Generate clock
 70     clk <= not clk after 10 ns;
 71     rst <= '0' after 3 ns;
 72 
 73     Inst_lfsr : lfsr_implement
 74     port map (
 75         clk    => clk,   
 76         rst    => rst,
 77         lfsr_1 => lfsr_1,
 78         lfsr_2 => lfsr_2
 79     );
 80 
 81    -- Display the time and result
 82     process (clk)
 83         variable wrbuf :line;
 84     begin
 85         if (clk = '1') then
 86             write(wrbuf, string'("Time: ")); write(wrbuf, now);
 87             write(wrbuf, string'("; lfsr_1: ")); write(wrbuf, conv_integer(lfsr_1));
 88             write(wrbuf, string'("; lfsr_2: ")); write(wrbuf, conv_integer(lfsr_2));
 89             writeline(output, wrbuf);
 90         end if;
 91     end process;
 92 
 93 end architecture;
You could download file vhdl_examples here
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com