1 //-----------------------------------------------------
  2 // Design Name : up_down_counter
  3 // File Name   : up_down_counter.v
  4 // Function    : Up down counter
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module up_down_counter    (
  8 out      ,  // Output of the counter
  9 up_down  ,  // up_down control for counter
 10 clk      ,  // clock input
 11 reset       // reset input
 12 );
 13 //----------Output Ports--------------
 14 output [7:0] out;
 15 //------------Input Ports-------------- 
 16 input [7:0] data;
 17 input up_down, clk, reset;
 18 //------------Internal Variables--------
 19 reg [7:0] out;
 20 //-------------Code Starts Here-------
 21 always @(posedge clk)
 22 if (reset) begin // active high reset
 23   out <= 8'b0 ;
 24 end else if (up_down) begin
 25   out <= out + 1;
 26 end else begin
 27   out <= out - 1;
 28 end
 29 
 30 endmodule 

Copyright © 1998-2008

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com