1 //-----------------------------------------------------
  2 // Design Name : ram_sp_ar_sw
  3 // File Name   : ram_sp_ar_sw.v
  4 // Function    : Asynchronous read write RAM 
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module ram_sp_ar_sw (
  8 clk         , // Clock Input
  9 address     , // Address Input
 10 data        , // Data bi-directional
 11 cs          , // Chip Select
 12 we          , // Write Enable/Read Enable
 13 oe            // Output Enable
 14 ); 
 15 
 16 parameter DATA_WIDTH = 8 ;
 17 parameter ADDR_WIDTH = 8 ;
 18 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
 19 
 20 //--------------Input Ports----------------------- 
 21 input                                     clk          ;
 22 input [ADDR_WIDTH-1:0] address ;
 23 input                                     cs           ;
 24 input                                     we          ;
 25 input                                     oe           ; 
 26 
 27 //--------------Inout Ports----------------------- 
 28 inout [DATA_WIDTH-1:0]  data       ;
 29 
 30 //--------------Internal variables---------------- 
 31 reg [DATA_WIDTH-1:0]   data_out ;
 32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
 33 
 34 //--------------Code Starts Here------------------ 
 35 
 36 // Tri-State Buffer control 
 37 // output : When we = 0, oe = 1, cs = 1
 38 assign data = (cs && oe &&  ! we) ? data_out : 8'bz; 
 39 
 40 // Memory Write Block 
 41 // Write Operation : When we = 1, cs = 1
 42 always @ (posedge clk)
 43 begin : MEM_WRITE
 44    if ( cs && we ) begin
 45        mem[address] = data;
 46    end
 47 end
 48 
 49 // Memory Read Block 
 50 // Read Operation : When we = 0, oe = 1, cs = 1
 51 always @ (address or cs or we or oe)
 52 begin : MEM_READ
 53     if (cs &&  ! we && oe) begin
 54          data_out = mem[address];
 55     end
 56 end
 57 
 58 endmodule // End of Module ram_sp_ar_sw

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Deepak Kumar Tala - All rights reserved

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