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1 module t_gate_switch (L,R,nC,C);
2 inout L;
3 inout R;
4 input nC;
5 input C;
6
7 //Syntax: keyword unique_name (drain. source, gate);
8 pmos p1 (L,R,nC);
9 nmos p2 (L,R,C);
10
11 endmodule
You could download file t_gate_switch.v here
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1 module misc1 (a,b,c,d,y);
2 input a, b,c,d;
3 output y;
4
5 wire net1,net2,net3;
6
7 supply1 vdd;
8 supply0 vss;
9
10 // y = !((a+b+c).d)
11
12 pmos p1 (vdd,net1,a);
13 pmos p2 (net1,net2,b);
14 pmos p3 (net2,y,c);
15 pmos p4 (vdd,y,d);
16
17 nmos n1 (vss,net3,a);
18 nmos n2 (vss,net3,b);
19 nmos n3 (vss,net3,c);
20 nmos n4 (net3,y,d);
21
22 endmodule
You could download file misc1.v here
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