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  ../../images/main/bullet_green_ball.gif Divide by 2 Counter
   

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  1 //-----------------------------------------------------
  2 // Design Name : clk_div
  3 // File Name   : clk_div.v
  4 // Function    : Divide by two counter
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 
  8 module clk_div (clk_in, enable,reset, clk_out);
  9  // --------------Port Declaration----------------------- 
 10  input               clk_in                   ;
 11  input               reset                    ;
 12  input               enable                   ;
 13  output              clk_out                  ;
 14  //--------------Port data type declaration-------------
 15  wire                 clk_in                  ;
 16  wire                 enable                  ;
 17 //--------------Internal Registers----------------------
 18 reg                   clk_out                 ;
 19 //--------------Code Starts Here----------------------- 
 20 always @ (posedge clk_in) 
 21 if (reset) begin 
 22   clk_out <= 1'b0;
 23 end else if (enable) begin
 24   clk_out <=  ! clk_out ; 
 25 end
 26 
 27 endmodule  
You could download file clk_div.v here
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com