-------------------------------------------------------
-- Design Name : clk_div_45
-- File Name   : clk_div_45.vhd
-- Function    : Divide by 4.5
-- Coder       : Deepak Kumar Tala (Verilog)
-- Translator  : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity clk_div_45 is
    port (
        cout   :out std_logic;  -- Output clock
        enable :in  std_logic;  -- Enable counting
        clk    :in  std_logic;  -- Input clock
        reset  :in  std_logic   -- Input reset
    );
end entity;

architecture rtl of clk_div_45 is
    signal counter1 :std_logic_vector (2 downto 0);
    signal counter2 :std_logic_vector (2 downto 0);
    signal toggle1  :std_logic;
    signal toggle2  :std_logic;

begin
    process (clk) begin
        if (rising_edge(clk)) then
            if (enable = '0') then
                counter1 <= (others=>'0');
                toggle1  <= '0';
            elsif ((counter1 = 3 and toggle2 = '1') or
                   (toggle1 = '0' and counter1 = 4)) then
                counter1 <= (others=>'0');
                toggle1  <= not toggle1;
            else
                counter1 <= counter1 + 1;
            end if;
        end if;
    end process;

    process (clk) begin
        if (falling_edge(clk)) then
            if (enable = '0') then
                counter2 <= (others=>'0');
                toggle2  <= '0';
            elsif ((counter2 = 3 and toggle2 = '0') or
                   (toggle2 = '1' and counter2 = 4)) then
                counter2 <= (others=>'0');
                toggle2  <= not toggle2;
            else
                counter2 <= counter2 + 1;
            end if;
        end if;
    end process;
    cout <= enable when (counter1 < 3 and counter2 < 3) else
            '0';
end architecture;