library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all; 

entity counter_tb is
end;

architecture counter_tb of counter_tb is

COMPONENT counter
  PORT ( count : OUT std_logic_vector(3 downto 0);
         clk   : IN std_logic;
         enable: IN std_logic;
         reset : IN std_logic);
END COMPONENT ;

SIGNAL   clk    : std_logic := '0';
SIGNAL   reset  : std_logic := '0';
SIGNAL   enable : std_logic := '0';
SIGNAL   count  : std_logic_vector(3 downto 0);

begin

dut : counter 
PORT MAP (
   count => count,
   clk   => clk,
   enable=> enable,
   reset => reset );

  clock : PROCESS
  begin
     wait for 1 ns; clk  <= not clk;
  end PROCESS clock;

  stimulus : PROCESS
  begin
    wait for 5 ns; reset  <= '1';
    wait for 4 ns; reset  <= '0';
    wait for 4 ns; enable <= '1';
    wait;
  end PROCESS stimulus;

  monitor : PROCESS (clk)
  variable c_str : line;
  begin
    if (clk = '1' and clk'event) then
      write(c_str,count);
      assert false report time'image(now) & 
        ": Current Count Value : " & c_str.all
      severity note;
      deallocate(c_str);
    end if;
  end PROCESS monitor;

end counter_tb;