module sample_if_verilog ();
// Internal variables
reg [3:0] counter;
reg       clk;
wire      rst;
wire      counter_en;
wire      data;
wire      ddr_data_in;
wire      ddr_data_out;

assign data = (counter[2]) ? counter[0] : counter[1];
assign ddr_data_in = (clk) ? counter[0] : counter[1];

// Connect the program here
interface_ex vshell(
 .SystemClock            (clk),
 .\sample_if.clock       (clk),
 .\sample_if.reset       (rst),
 .\sample_if.enable      (counter_en),
 .\sample_if.cout        (counter),
 .\sample_if.data        (data),
 .\sample_if.ddr_data_in (ddr_data_in)
);
// Init all the variables
initial begin
  clk = 0;
end
// Clock generator
always #1 clk = ~clk;
// Counter code
always @ (posedge clk)
  if (rst) counter <= 0;
  else if (counter_en) counter <= counter + 1;

endmodule