#include "vera_defines.vrh"

interface sample_if {
 // Other signals are sampled with respect to this
 input clock          CLOCK; 
 output reset         PHOLD#1;
 output enable        PHOLD#1;
 input [7:0] cout     PSAMPLE #-1;
 inout data           PSAMPLE PHOLD NSAMPLE#-1 NHOLD #1;
 input ddr_data_in    PSAMPLE NSAMPLE;
 input data_in        PSAMPLE #-1 hdl_node "sample_if_verilog.data";
 input [7:0] count    PSAMPLE #-1 hdl_node "sample_if_verilog.counter";
 output  nenable      PHOLD   #1 hdl_node "sample_if_verilog.counter_en";
}

program interface_ex {
     // Start the actual test here
   @ (posedge sample_if.clock);
   printf("Asserting Reset\n");
   sample_if.reset = 1;
   sample_if.enable = 0;
   @ (posedge sample_if.clock);
   printf("Deasserting Reset\n");
   sample_if.reset = 0;
   @ (posedge sample_if.clock);
   printf("Asserting Enable\n");
   sample_if.enable = 1;
   repeat(10) {
     @ (posedge sample_if.clock);
     printf("Counter value %x\n",sample_if.cout);
     printf("DDR sample pos %x\n",sample_if.ddr_data_in);
     @ (negedge sample_if.clock);
     printf("DDR sample neg %x\n",sample_if.ddr_data_in);
   }
   @ (posedge sample_if.clock);
   printf("Deasserting Enable\n");
   sample_if.enable = 0;
}