module hdl_node_verilog ();
// Internal variables
reg [3:0] counter;
reg       clk;
wire      rst;
wire      counter_en;


// Connect the program here
hdl_node_ex vshell(
 .SystemClock            (clk)
);
// Init all the variables
initial begin
  clk = 0;
end
// Clock generator
always #1 clk = ~clk;
// Counter code
always @ (posedge clk)
  if (rst) counter <= 0;
  else if (counter_en) counter <= counter + 1;

endmodule