#include "vera_defines.vrh"

interface hdl_node_if {
 // Other signals are sampled with respect to this
 input clock          CLOCK      hdl_node "hdl_node_verilog.clk"; 
 output reset         PHOLD#1    hdl_node "hdl_node_verilog.rst";
 output enable        PHOLD#1    hdl_node "hdl_node_verilog.counter_en";
 input [7:0] cout     PSAMPLE#-1 hdl_node "hdl_node_verilog.counter";
}

program hdl_node_ex {
     // Start the actual test here
   @ (posedge hdl_node_if.clock);
   printf("Asserting Reset\n");
   hdl_node_if.reset = 1;
   hdl_node_if.enable = 0;
   @ (posedge hdl_node_if.clock);
   printf("Deasserting Reset\n");
   hdl_node_if.reset = 0;
   @ (posedge hdl_node_if.clock);
   printf("Asserting Enable\n");
   hdl_node_if.enable = 1;
   repeat(10) {
     @ (posedge hdl_node_if.clock);
     printf("Counter value %x\n",hdl_node_if.cout);
   }
   @ (posedge hdl_node_if.clock);
   printf("Deasserting Enable\n");
   hdl_node_if.enable = 0;
}