// Simple Verilog Memory Model
module memory(
address,     // Address bus port
data_in,     // Data input port
data_out,    // Data output port
read_write,  // Read/Write Enable
chip_en      // Chip select
);

input [7:0] address;
input [31:0] data_in;
output [31:0] data_out;
input read_write, chip_en;

reg [31:0] mem [0:255];

always @ (address or data_in or read_write or chip_en)
if (read_write == 1 && chip_en == 1) begin
  mem[address] = data_in;
end

assign data_out = (read_write == 0 && chip_en == 1) ? mem[address] : 0;

endmodule

// Top level testbench code
module tb();

// All the signals that need to be driven from
// SystemC testbench needs be declared as reg
reg [7:0] addr;
reg [31:0] wdata;
wire [31:0] rdata;
reg         wr;
reg         cs;
reg         clk;

// Connect the Verilog Memory DUT
memory dut (addr,wdata,rdata,wr,cs);

initial begin
  clk = 0;
  // Connect the systemC testbench here
  $memory_tb(clk,rdata,addr,wr,cs,wdata);
  $dumpfile("memory.vcd");
  $dumpvars();
end
// Clock generator
always #1 clk = ~clk;

endmodule