//-----------------------------------------------------
// Design Name : gray_counter
// File Name   : gray_counter.sv
// Function    : 8 bit gray counter
// Coder      : Deepak
//-----------------------------------------------------
module gray_counter (
output wire [7:0] out    , // counter out
input  wire       enable , // enable for counter
input  wire       clk    , // clock
input  wire       rst      // active hight reset
);
//------------Internal Variables--------
reg [7:0] count;
//-------------Code Starts Here---------
always_ff @ (posedge clk) 
if (rst) begin
  count <= 0; 
end else if (enable) begin 
  count <= count + 1; 
end
  
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ 
             count[5]),(count[5] ^ count[4]), (count[4] ^ 
             count[3]),(count[3] ^ count[2]), (count[2] ^ 
             count[1]),(count[1] ^ count[0]) };
  
endmodule