//-----------------------------------------------------
// Design Name : divide_by_3 
// File Name   : divide_by_3.sv
// Function    : Divide By 3
// Coder       : Deepak Kumar Tala
//-----------------------------------------------------
module divide_by_3 (
input   wire   clk_in       , //Input Clock
input   wire   reset        , // Reset Input
output  wire   clk_out        // Output Clock
);
//------------Internal Variables--------
reg [1:0] pos_cnt;
reg [1:0] neg_cnt;
//-------------Code Start-----------------
// Posedge counter
always_ff @ (posedge clk_in)
if (reset) begin
  pos_cnt <= 0;
end else begin
  pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
end
// Neg edge counter
always_ff @ (negedge clk_in)
if (reset) begin
  neg_cnt <= 0;
end else begin
  neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
end

assign clk_out = ((pos_cnt != 2) && (neg_cnt != 2));

endmodule