//-----------------------------------------------------
// Design Name : clk_div
// File Name   : clk_div.sv
// Function    : Divide by two counter
// Coder      : Deepak Kumar Tala
//-----------------------------------------------------
module clk_div (
input  wire  clk_in, 
input  wire  enable,
input  wire  reset, 
output reg   clk_out
);
//--------------Code Starts Here----------------------- 
always_ff @ (posedge clk_in) 
if (reset) begin 
  clk_out <= 1'b0;
end else if (enable) begin
  clk_out <= !clk_out ; 
end

endmodule