<'
struct uart_txgen {
   sb : uart_sb;

   !tx_done      : bit;
   !rx_done      : bit;

   loopback     : bit;
     keep loopback == 0;
   no_tx_cmds   : uint;
     keep no_tx_cmds == 1;
   no_rx_cmds   : uint;
     keep no_rx_cmds == 1;
   rx_over_flow : bit;
     keep rx_over_flow == 0;
   tx_over_flow : bit;
     keep tx_over_flow == 0;
   tx_frame_err : bit;
     keep tx_frame_err == 0;
   
   goTxgen()@sys.any is {
     tx_done = 0;
     rx_done = 0;
     assertReset();
     start tx();
     start rx();
     start txMonitor();
     start rxMonitor();
   };

   assertReset()@sys.rxclk is {
      wait cycle;
      'top.reset' = 1;
      outf("%dns : Asserting reset to Uart\n",sys.time);
      wait [5]*cycle;
      'top.reset' = 0;
   };

   tx()@sys.txclk is {
     var tx_timeout : uint = 0;
     var tx_data : byte = 0;
     'top.tx_enable' = 1;
     for {var i : uint = 0; i < no_tx_cmds; i = i + 1} do {
       gen tx_data;
       sb.txAdd(tx_data);
       if (loopback == 1) {
         sb.rxAdd(tx_data);
       };
       // Check if uart is ready to accept data for transmission
       while ('top.tx_empty' == 0) {
         wait cycle;
         tx_timeout =+ 1 ;
         if (tx_timeout > 10) {
           outf("%dns : txDriver : Warning : tx_empty is 0 for more then 10 clocks\n",sys.time);
         };
       };
       tx_timeout = 0;
       // Drive the data in UART for transmitting
       wait cycle;
       'top.ld_tx_data' = 1;
       'top.tx_data'    = tx_data;
       outf("%dns : txDriver : Transmitting data %x\n",sys.time, tx_data);
       wait cycle;
       'top.ld_tx_data' = 0;
       'top.tx_data'    = 0;
       while ('top.tx_empty' == 1) {
         wait cycle;
         tx_timeout =+ 1 ;
         if (tx_timeout > 10) {
           outf("%dns : txDriver : Warning : tx_empty is 1 for more then 10 clocks\n",sys.time);
         };
       };
       tx_timeout = 0;
     };
     tx_done = 1;
   };

   rx()@sys.txclk is {
     var rx_data : byte = 0;
     'top.rx_enable' = 1;
     if (loopback == 1) {
       'top.loopback' = 1;
     } else {
       'top.loopback' = 0;
       for {var i : uint = 0; i < no_rx_cmds; i = i + 1} do {
         gen rx_data; 
         sb.rxAdd(rx_data);
         outf("%dns : rxDriver : Transmitting data %x\n",sys.time, rx_data);
         wait cycle;
         'top.rx_in' = 0;
         for {var j : uint = 0; j < 8; j = j + 1} do {
           wait cycle;
           'top.rx_in' = rx_data[j:j];
         };
         wait cycle;
         'top.rx_in' = 1;
         wait cycle;
       };
     };
     rx_done = 1;
   };

   txMonitor()@sys.txclk is {
     var tx_data : byte = 0;
     while (TRUE) {
       wait cycle;
       if ('top.tx_out' == 0) {
          outf("%dns : txMonitor : Found start of frame\n",sys.time);
          for {var i : uint = 0; i < 8; i = i + 1} do {
            wait cycle;
            tx_data[i:i] = 'top.tx_out';
          };
          wait cycle;
          if ('top.tx_out' == 0) {
            outf("%dns : txMonitor Error : Framing error detecting\n",sys.time);
            sb.txCompare(8'b0);
          } else {
            outf("%dns : txMonitor : Sampled data %x\n",sys.time, tx_data);
            sb.txCompare(tx_data);
          };
       };
     };
   };

   rxMonitor()@sys.rxclk is {
     var rx_data : byte = 0;
     while (TRUE) {
       wait cycle;
       if ('top.rx_empty' == 0) {
         'top.uld_rx_data' = 1;
         wait cycle;
         rx_data = 'top.rx_data';
         'top.uld_rx_data' = 0;
         outf("%dns : rxMonitor : Sampled data %x\n",sys.time, rx_data);
         sb.rxCompare(rx_data);
         wait cycle;
       };
     };
   };
   
   isDone() : bool is {
     var status : bool = FALSE;
     if (tx_done == 1 && rx_done == 1) {
       status =  TRUE;
     };
     return status;
   };
};
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