`include "uart.v"
module top();

reg        reset          ;
reg        txclk          ;
reg        ld_tx_data     ;
reg  [7:0] tx_data        ;
reg        tx_enable      ;
wire       tx_out         ;
wire       tx_empty       ;
reg        rxclk          ;
reg        uld_rx_data    ;
wire [7:0] rx_data        ;
reg        rx_enable      ;
wire       rx_in          ;
wire       rx_empty       ;
reg        loopback       ; 
reg        rx_tb_in       ;

initial begin
  reset       = 0;
  txclk       = 0;
  ld_tx_data  = 0;
  tx_data     = 0;
  tx_enable   = 0;
  rxclk       = 0;
  uld_rx_data = 0;
  rx_enable   = 0;
  loopback    = 0;
  rx_tb_in    = 1;
end
// Loopback control logic
assign rx_in = (loopback) ? tx_out : rx_tb_in;
// RX and TX Clock generation
always #1 rxclk = ~rxclk;
always #16 txclk = ~txclk;

// DUT Connected here
uart U (
.reset          (reset),
.txclk          (txclk),
.ld_tx_data     (ld_tx_data),
.tx_data        (tx_data),
.tx_enable      (tx_enable),
.tx_out         (tx_out),
.tx_empty       (tx_empty),
.rxclk          (rxclk),
.uld_rx_data    (uld_rx_data),
.rx_data        (rx_data),
.rx_enable      (rx_enable),
.rx_in          (rx_in),
.rx_empty       (rx_empty)
);

endmodule