<'
unit mem_driver {
  event clk is rise('top.mem_clk') @sim; 
  // This method drives the DUT
  drive_mem(mem_base : mem_object)@clk is {
    wait cycle;
    //Driver ce,addr,rd_wr command
    'top.mem_ce' = 1;
    'top.mem_addr' = mem_base.addr;
    'top.mem_rd_wr' = mem_base.rd_wr;
    if (mem_base.rd_wr == FALSE) {
      'top.mem_wr_data' = mem_base.data;
    };
    // Deassert all the driven signals
    wait cycle;
    'top.mem_ce' = 0;
    'top.mem_addr' = 0;
    'top.mem_rd_wr' = 0;
    'top.mem_wr_data' = 0;
  };
};
'>