`include "switch_fabric.v"

module unit_example();

reg  clk, reset;
reg  [7:0] data_in0, data_in1, data_in2, data_in3;
reg  [7:0] data_in4, data_in5;
reg  data_in_valid0, data_in_valid1, data_in_valid2;
reg  data_in_valid3, data_in_valid4, data_in_valid5;
wire [7:0] data_out0, data_out1, data_out2; 
wire [7:0] data_out3, data_out4, data_out5;
wire data_out_ack0, data_out_ack1, data_out_ack2;
wire data_out_ack3, data_out_ack4, data_out_ack5;

initial begin
  clk = 0;
  reset = 0;
  #10 reset = 1;
  #10 reset = 0;
  data_in0  = 0;       
  data_in1  = 0;
  data_in2  = 0;
  data_in3  = 0;
  data_in4  = 0;
  data_in5  = 0;
  data_in_valid0  = 0;
  data_in_valid1  = 0;
  data_in_valid2  = 0;
  data_in_valid3  = 0;
  data_in_valid4  = 0;
  data_in_valid5  = 0;
end

always #2.5 clk = ~clk;

switch_fabric U_switch_fabric(
 .clk(clk), .reset(reset),
 .data_in0(data_in0), .data_in1(data_in1),
 .data_in2(data_in2), .data_in3(data_in3),
 .data_in4(data_in4), .data_in5(data_in5),
 .data_in_valid0(data_in_valid0), .data_in_valid1(data_in_valid1),
 .data_in_valid2(data_in_valid2), .data_in_valid3(data_in_valid3),
 .data_in_valid4(data_in_valid4), .data_in_valid5(data_in_valid5),
 .data_out0(data_out0), .data_out1(data_out1),
 .data_out2(data_out2), .data_out3(data_out3),
 .data_out4(data_out4), .data_out5(data_out5),
 .data_out_ack0(data_out_ack0), .data_out_ack1(data_out_ack1),
 .data_out_ack2(data_out_ack2), .data_out_ack3(data_out_ack3),
 .data_out_ack4(data_out_ack4), .data_out_ack5(data_out_ack5)
);

endmodule